COP8CCE9IMT7SLASHNOPB datasheet(39/101 Pages) TI1

39 / 101 page

COP8CCE9

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SNOS978J – JUNE 2001 – REVISED MARCH 2013

Figure 18. Functional Block Diagram for Idle Timer T0

Table 16. Idle Timer Window Length

Idle Timer Period

ITSEL2

ITSEL1

ITSEL0

High Speed

Dual Clock or

Mode

Low Speed Mode

4,096 inst. cycles

0.125 seconds

8,192 inst. cycles

0.25 seconds

16,384 inst. cycles

0.5 seconds

32,768 inst. cycles

1 second

65,536 inst. cycles

2 seconds

Reserved - Undefined

The ITSEL bits of the ITMR register are cleared on Reset and the Idle Timer period is reset to 4,096 instruction

cycles.

ITMR Register

CCK

LSON

HSON

DCEN

RSVD

ITSEL2

ITSEL1

ITSEL0

SEL

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bits 7–4: Described in Power Saving Features .

Note: Documentation for previous COP8 devices, which included the Programmable Idle Timer, recommended

the user write zero to the high order bits of the ITMR Register. If existing programs are updated to use this

device, writing zero to these bits will cause the device to reset (see Power Saving Features ).

RSVD: This bit is reserved and must be set to 0.

ITSEL2:0: Selects the Idle Timer period as described in Table 16 , Idle Timer Window Length.

Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer interrupt

by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing the value of the

ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to synchronize operation to the

IDLE Timer.

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