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AD9786BSV Datasheet(PDF) 46 Page - Analog Devices |
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AD9786BSV Datasheet(HTML) 46 Page - Analog Devices |
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46 / 60 page ![]() AD9786 Rev. 0 | Page 46 of 60 DATA INPUTS Digital data inputs to the AD9786 are accessed on the evaluation board through connectors J1 and J2. These are 40 pin right angle connectors that are intended to be used with standard ribbon cable connectors. The input levels should be either 3.3 V or 2.5 V CMOS, depending on the setting of the DRVDD jumper JP1. The data format is selectable through Register 02h, Bit 7 (DATAFMT). With this bit set to a default 0, the AD9786 assumes that the input data is in twos complement format. With this bit set to 1, data should be input in offset binary format. When the evaluation board is first powered up and the clock and data are running, it is recommended that the proper operating current is verified. Depress reset switch SW1 to ensure that the AD9786 is in the default mode. The default mode for the AD9786 is for the interpolation set to 1×. The modulator is turned off in the default mode. The nominal operating currents for the evaluation board in the power-up default mode are shown in Table 39. Additionally, the DRVDD power supply on the AD9786 is used to supply power for the digital input bus. DRVDD can be run from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper selectable by JP1, just to the left of the chip on the evaluation board. With the jumper set to the 3.3 V position, DRVDD chip receives its power from VDD3IN. With the jumper set to the 2.5 V position, DRVDD receives its power from AVDIN. SERIAL PORT SW1 is a hard reset switch that sets the AD9786 to its default state. It should be used every time the AD9786 power supply is cycled or the clock is interrupted, or if new data is to be written via the SPI port. Set the SPI software to read back data from the AD9786 and verify that when the software is run, the expected values are read back. Table 39. Nominal Operating Currents in Power-Up Default Mode Nominal Current @ Speed (mA) Evaluation Board Power Supply 50 MSPS 100 MSPS 150 MSPS 200 MSPS DVDD 26 49 74 99 CLKVDD 78 83 87 92 ACVDD and ADVDD 1 4 6 8 AVDD1 30 30 30 30 AVDD2 27 27 27 27 Table 40. SPI Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 0 01h INTERP[1] INTERP[0] |
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