AD9786BSV datasheet(28/60 Pages) AD

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AD9786

Rev. 0 | Page 28 of 60

AD9786 DATACLK Slave Mode, Data Recovery On

DATACLK (Pin 31) can be used as an input in order to

synchronize multiple AD9786s. A clock generated by an

AD9786 operating in master mode, or a clock from an external

source, can be used to drive DATACLK.

In this mode, there are two clocks required to be applied to the

AD9786. A clock running at the DAC sample rate, referred to as

DACCLK, must be applied to the differential inputs (Pins 5 and

6) of the AD9786. As described above, a clock at the input

sample rate must also be applied to Pin 31 (DATACLK). An

internal DLL synchronizes the two applied clocks. The timing

relationships between the input data, DATACLK, and DACCLK

are given in Figure 49 and Figure 50.

Note that DCLKPOL (Reg 02h, Bit 4) can be used to select the

edge of DACCLK upon which the input data is latched.

There is a defined setup and hold window with respect to input

data and the latching edge of DACCLK. There is also a required

timing relationship between DATACLK and DACCLK. This is

referred to in Figure 49 and Figure 50 as tST and tHT (setup and

hold for transition). As an example, with DCLKPOL set to

logic 0, the input data will latch on the first rising edge of

DACCLK which occurs greater than 1.5 ns before the falling

edge of DATACLK. DACCLK should not be given a rising edge

in the window of 500 ps to 1.5 ns before the latching edge

(falling when DCLKPOL = 0, rising when DCLKPOL = 1) of

DATACLK. Failure to account for this timing relationship may

result in corrupt data.

There are three status bits available for read which allow the

user to verify DLL lock. These are Bits 0, 1, and 2 (DCRCSTAT)

in Reg 12h.

DACCLKIN

DATACLKIN

DATA

tHT = 1.5ns MIN

tS = 0.0ns MIN

tST = –500ps MIN

tH = 3.2ns MIN

Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0

DACCLKIN

DATACLKIN

DATA

tHT = 2.0ns MIN

tS = 0.0ns MIN

tST = –1.0ns MIN

tH = 3.2ns MIN

Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1

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