DP83905 datasheet(52/80 Pages) NSC

52 / 80 page

60 Operation of ATLANTIC Controller (Continued)

loopback testing When loopback mode is selected in the

TCR the FIFO is spilt A packet should be assembled in

memory with programming of TPSR and TBCR0 TBCR1

registers When the transmit command is issued the follow-

ing operations occur

TRANSMITTER ACTIONS

1 Data is transferred from memory by the DMA until the

FIFO is filled For each transfer TBCR0 and TBCR1 are

decremented (Subsequent burst transfers are initiated

when the number of bytes in the FIFO drops below the

programmed threshold)

2 The ATLANTIC Controller generates 56 bits of pream-

ble followed by an 8-bit synch pattern

3 Data transferred from FIFO to serializer

4 If CRC e 1 in TCR no CRC calculated by ATLANTIC

Controller the last byte transmitted is the last byte from

the FIFO (allows software CRC to be appended) If

CRC e 0 ATLANTIC Controller calculates and ap-

pends four bytes of CRC

5 At end of Transmission PTX bit set in ISR

RECEIVER ACTIONS

1 Wait for synch all preamble stripped

2 Store packet in FIFO increment receive byte count for

each incoming byte

3 If CRC e 0 in TRC receiver checks incoming packet for

CRC errors If CRC e 1 in TCR receiver does not check

CRC errors CRC error bit always set in RSR (for address

matching packets)

4 At end of receive receive byte count written into FIFO

receive status register is updated The PRX bit is typically

set in the RSR even if the address does not match If

CRC errors are forced the packet must match the ad-

dress filters in order for the CRC error bit in the RS to be

set

EXAMPLES

The following examples show what results can be expected

from a properly operating ATLANTIC Controller during

loopback The restrictions and results of each type of Ioop-

back are listed for reference The loopback tests are divided

into two sets of tests One to verify the data path CRC

generation and byte count through all three paths The sec-

ond set of tests uses internal loopback to verify the receiv-

er’s CRC checking and address recognition For all of the

tests the DCR was programmed to 40H

Path

TCR RCR

TSR

RSR

ISR

ATLANTIC

Controller

(Note 1) (Note 2) (Note 3)

Internal

Note 1

Since carrier sense and collision detect are generated in the

ENDEC module They are blocked during internal loopback carrier

and CD heartbeat are not seen and the CRS and CDH bits are set

Note 2

CRC errors are always indicated by receiver if CRC is appended by

the transmitter

Note 3

Only the PTX bit in the ISR is set the PRX bit is only set if status is

written to memory In loopback this action does not occur and the

PRx bit remains 0 for all loopback modes

Note 4

All values are hex

Path

TCR

RCR

TSR

RSR

ISR

ATLANTIC

Controller

(Note 1)

Internal

Note 1

CDH is set CRS is not set since it is generated by the external

encoderdecoder

Path

TCR

RCR

TSR

RSR

ISR

ATLANTIC

Controller

(Note 1)

(Note 2)

External

Note 1

CDH and CRS should not be set The TSR however could also

contain 01H03H07H and a variety of other values depending on

whether collisions were encountered or the packet was deferred

Note 2

Will contain 08H if packet is not transmittable

Note 3

During extemal loopback the ATLANTIC Controller is now ex-

posed to network traffic it is therefore possible for the contents of

both the Receive portion of the FIFO and the RSR to be corrupted

by any other packet on the network Thus in a live network the

contents of the FIFO and RSR should not be depended on The

ATLANTIC Controller will still abide by the standard CSMACD

protocol in external loopback mode (ie the network will not be

disturbed by the loopback packet)

Note 4

All values are hex

CRC and Address Recognition

The next three tests exercise the address recognition logic

and CRC These tests should be performed using internal

Ioopback only so that the ATLANTIC Controller is isolated

from interference from the network These tests also require

the capability to generate CRC in software

The address recognition logic cannot be directly tested The

CRC and FAE bits in the RSR are only set if the address in

the packet matches the address filters If errors are expect-

ed to be set and they are not set the packet has been

rejected on the basis of an address mismatch The following

sequence of packets will test the address recognition logic

The DCR should be set to 40H the TCR should be set to

03H with a software generated CRC

Packet Contents

Results

Test

Address

CRC

RSR

Test A

Matching

Good

01 (Note 1)

Test B

Matching

Bad

02 (Note 2)

Test C

Non-Matching

Bad

Note 1

Status will read 21H if multicast address used

Note 2

Status will read 22H if multicast address used

Note 3

In test A the RSR is set up In test B the address is found to match

since the CRC is flagged as bad Test C proves that the address

recognition logic can distinguish a bad address and does not notify

the RSR of the bad CRC The receiving CRC is proven to work in

test A and test B

Note 4

All values are hex

DP83905 Datasheet(PDF) 52 Page - National Semiconductor (TI)

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