DP83905 datasheet(17/80 Pages) NSC

17 / 80 page

40 Functional Description (Continued)

TLF11498 – 9

FIGURE 12 DP8390 Controller Core Simplified Block Diagram

Transmit Serializer

The Transmit Serializer reads parallel data from the FIFO

and serializes it for transmission The serializer is clocked by

the transmit clock generated internally The serial data is

also shifted into the CRC generatorchecker At the begin-

ning of each transmission the Preamble and Synch Gener-

ator append 62 bits of 10 preamble and a 11 synch pat-

tern After the last data byte of the packet has been serial-

ized the 32-bit FCS (Frame Check Sequence) field is shifted

directly out of the CRC generator In the event of a collision

the Preamble and Synch generator is used to generate a

32-bit JAM pattern of all 1’s

Comparator-address Recognition Logic

The address recognition logic compares the Destination Ad-

dress Field (first 6 bytes of the received packet) to the Phys-

ical address registers stored in the Address Register Array

If any one of the six bytes does not match the pre-pro-

grammed physical address the Protocol Control Logic re-

jects the packet All multicast destination addresses are fil-

tered using a hashing technique (See register description)

If the multicast address indexes a bit that has been set in

the filter bit array of the Multicast Address Register Array

the packet is accepted otherwise it is rejected by the Proto-

col Control Logic Each destination address is also checked

for all 1’s which is the reserved broadcast address

FIFO and Packet Data Operations

OVERVIEW

To accommodate the different rates at which data comes

from (or goes to) the network and goes to (or comes from)

the packet buffer memory the ATLANTIC Controller con-

tains a 16-byte FIFO for buffering data between the media

and the buffer RAM located on the memory support bus

The FIFO threshold is programmable allowing filling (or

emptying) the FIFO at different rates When the FIFO has

filled to its programmed threshold the local DMA channel

transfers these bytes (or words) into local memory (via the

memory bus) It is crucial that the local DMA is given access

to the bus within a minimum bus latency time otherwise a

FIFO underrun (or overrun) occurs

FIFO underruns or overruns are caused when a local DMA

request is issued while an ISA bus access is current and the

ISA cycle takes longer to complete than the local DMA’s

tolerable latency This tolerable latency depends on the

FIFO threshold whether it is in byte or word wide mode and

the speed of the DMA clock (BSCLK frequency) Note that

this refers to standard ISA cycles NOT those where the

CHRDY is deasserted extending the cycle

FIFO THRESHOLD DETECTION

To assure that there is no overwriting of data in the FIFO

the FIFO logic flags a FIFO overrun as the 13th byte is

written into the FIFO effectively shortening the FIFO to 13

bytes The FIFO logic also operates differently in Byte Mode

and in Word Mode In Byte Mode a threshold is indicated

when the na1 byte has entered the FIFO thus with an 8

byte threshold the ATLANTIC Controller issues a request

to the buffer RAM when the 9th byte has entered the FIFO

making the effective threshold 9 bytes For Word Mode the

request is not generated until the na2 bytes have entered

the FIFO Thus with a 4 word threshold (equivalent to 8

byte threshold) a request to the buffer RAM is issued when

the 10th byte has entered the FIFO making the effective

threshold 10 bytes

TOLERABLE LATENCY CALCULATION

To prevent a FIFO overrun a byte (or word) of data must be

removed

from the FIFO before the 13th byte is written

Therefore the worst case tolerable latency is the time from

the effective threshold being reached to the time the 13th

byte is written minus the time taken to load the first byte (or

word) of data to the FIFO during a local DMA burst (8

BSCLKs)

tolerable latency e ((overrun b effective) threshold

time to transfer byte on network)

time to fill 1st FIFO location

DP83905 Datasheet(PDF) 17 Page - National Semiconductor (TI)

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