DP83905 datasheet(18/80 Pages) NSC

18 / 80 page

40 Functional Description (Continued)

For the case of a 4 word threshold using a 20 MHz BSCLK

tolerable latency e ((13 b 10) c 800) b (8 c 50) ns

2 ms

To prevent a FIFO underrun a byte (or word) of data must

be added from the FIFO before the last byte is removed

Therefore the worst case tolerable latency is the time from

the effective threshold being reached to the time the last

byte is removed minus the time taken to load the first byte

(or word) of data to the FIFO during a local DMA burst (8

BSCLKs)

tolerable latency e (threshold

time to transfer byte on network)

time to fill 1st FIFO location

For the case of a 4 word threshold using a 20 MHz BSCLK

tolerable latency e (4 c 800) b (8 c 50) ns

28 ms

The worst case latency either overrun or underrun ulti-

mately limits the overall latency that the ATLANTIC Con-

troller can tolerate If the standard ISA cycles are shorter

than the worst case latency then no FIFO overruns or un-

derruns will occur

BEGINNING OF RECEIVE

At the beginning or reception the ATLANTIC Controller

stores entire Address field of each incoming packet in the

FIFO to determine whether the packet matches its Physical

Address Registers or maps to one of its Multicast Registers

This causes the FIFO to accumulate 8 bytes

Furthermore there are some synchronization delays in the

DMA PLA Thus the actual time that a request to access

the buffer RAM is asserted from the time the Start of Frame

Delimiter (SFD) is detected is 78 ms This operation affects

the bus latencies at 2 byte and 4 byte thresholds during the

first receive request since the FIFO must be filled to 8 bytes

(or 4 words) before issuing a request to the buffer RAM

END OF RECEIVE

When the end of a packet is detected by the ENDEC mod-

ule the ATLANTIC Controller enters its end of packet pro-

cessing sequence emptying its FIFO and writing the status

information at the beginning of the packet The ATLANTIC

Controller holds onto the memory bus for the entire se-

quence The longest time that local DMA will hold the buffer

RAM occurs when a packet ends just as the ATLANTIC

Controller performs its last FIFO burst The ATLANTIC

Controller in this case performs a programmed burst trans-

fer followed by flushing the remaining bytes in the FIFO and

completed by writing the header information to the buffer

memory The following steps occur during this sequence

1 ATLANTIC Controller issues request to access the

RAM because the FIFO threshold has been reached

2 During the burst packet ends resulting in the request

being extended

3 ATLANTIC Controller flushes remaining bytes from

FIFO

4 ATLANTIC Controller performs internal processing to

prepare for writing the header

5 ATLANTIC Controller writes 4-byte (2-word) header

6 ATLANTIC Controller de-asserts access to the buffer

RAM

BEGINNING OF TRANSMIT

Before transmitting the ATLANTIC Controller performs a

prefetch from memory to load the FIFO The number of

bytes prefetched is the programmed FIFO threshold The

next request to the buffer RAM is not issued until after the

ATLANTIC Controller actually begins transmitting data ie

after SFD

READING THE FIFO

If the FIFO is read during normal operation the ATLANTIC

Controller will ‘‘hang’’ the ISA bus by deasserting CHRDY

and never asserting it The FIFO should only be read during

loopback diagnostics when it will operate normally

PROTOCOL PLA

The Protocol PLA is responsible for implementing the IEEE

8023 protocol including collision recovery with random

backoff The Protocol PLA also formats packets during

transmission and strips preamble and synch during recep-

tion

DMA AND BUFFER CONTROL LOGIC

The DMA and Buffer Control Logic is used to control two

16-bit DMA channels During reception the Local DMA

stores packets in a receive buffer ring located in buffer

memory During transmission the Local DMA uses pro-

grammed pointer and length registers to transfer a packet

from local buffer memory to the FIFO

A second DMA channel is used when the ATLANTIC Con-

troller is used in IO Port mode This DMA is used as a slave

DMA to transfer data between the local buffer memory and

the host system The Local DMA and Remote DMA are in-

ternally arbitrated with the Local DMA channel having high-

est priority Both DMA channels use a common external bus

clock to generate all required bus timing External arbitration

is performed with a standard bus request bus acknowledge

handshake protocol

In the shared memory mode the Remote DMA is not used

because in this mode the system has direct readwrite ac-

cess to the buffer RAM

DP83905 Datasheet(PDF) 18 Page - National Semiconductor (TI)

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