ADS8364

6

SBAS219B

www.ti.com

SPEC

DESCRIPTION

MIN

MAX

UNITS

Conversion Time

3.2

µs

Acquistion Time

0.8

µs

Cycle Time of CLK

200

ns

Pulse Width CLK HIGH Time or LOW Time.

60

ns

Delay Time of Rising Edge of Clock After Falling Edge of HOLD (A,B,C)

10

ns

Pulse Width of HOLDX HIGH Time to be Recognized again

15

ns

30

ns

Pulse Width of HOLDX LOW Time

20

ns

30

ns

Pulse Width of RESET

20

ns

40

ns

Pulse Width of RD HIGH Time

30

ns

40

ns

Delay Time of First Hold After RESET

20

ns

40

ns

Delay Time of Falling Edge of RD After Falling Edge of CS

0

ns

Delay Time of Rising Edge of CS After Rising Edge of RD

0

ns

Pulse Width of RD and CS Both LOW Time

50

ns

70

ns

Pulse Width of RD HIGH Time

20

ns

40

ns

Delay Time of Data Valid After Falling Edge RD

40

ns

60

ns

Delay Time of Data Hold From Rising Edge of RD

5

ns

10

ns

Delay Time of RD HIGH After CS LOW

50

ns

60

ns

Delay Time of RD Low After Address Setup

10

ns

20

ns

(3) See timing diagram above. (4) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BYTE is 1, bits 15 through 8

appear on DB7-DB0. RD may remain LOW between changes in BYTE. (5) Only important when synchronization to clock is important.

TIMING CHARACTERISTICS TABLE

Timing Characteristics over recommended operating free-air temperature range T

f

TIMING CHARACTERISTICS

t

W6

t

D6

t

D4

t

D5

t

D7

t

W5

t

W1

t

D1

t

C1

t

W3

CONVERSION

t

CONV

ACQUISITION

t

ACQ

t

W2

Bits 15-8

Bits 7-0

Bits 15-8

Bits 7-0

CLK

HOLDX

EOC

CS

RD

D15-D8

D7-D0

BYTE

1

2

16

17

18

19

20

1

2