DP8391AV datasheet(7/12 Pages) NSC

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80 Switching Characteristics

VCC e 5V g5% TA e 0 Cto70 C for DIP and 0 Cto55 C for PCC (Note 2) (Continued)

Symbol

Parameter

Figure

Min

Typ

Max

Units

TRANSMIT SPECIFICATION

(Continued)

tTOd

Transmit Output Delay from Transmit Clock Rising Edge

tTOr

Transmit Output Rise Time (20% to 80%)

tTOf

Transmit Output Fall Time (80% to 20%)

tTOj

Transmit Output Jitter

025

tTOh

Transmit Output High Before Idle in Half Step Mode

200

tTOi

Transmit Output Idle Time in Half Step Mode

800

RECEIVE SPECIFICATION

tRCd

Receive Clock Duty Cycle at 50% (10 MHz)

tRCr

Receive Clock Rise Time (20% to 80%)

tRCf

Receive Clock Fall Time (80% to 20%)

tRDr

Receive Data Rise Time (20% to 80%)

tRDf

Receive Data Fall Time (80% to 20%)

tRDs

Receive Data Stable from Receive Clock Rising Edge

tCSon

Carrier Sense Turn On Delay

tCSoff

Carrier Sense Turn Off Delay

8 912

160

tDAT

Decoder Acquisition Time

180

tDrej

Differential Inputs Rejection Pulse Width (Squelch)

tRd

Receive Throughput Delay

150

COLLISION SPECIFICATION

tCOLon

Collision Turn On Delay

tCOLoff

Collision Turn Off Delay

350

LOOPBACK SPECIFICATION

tLBs

Loopback Setup Time

tLBh

Loopback Hold Time

Note 2

All typicals are given for VCC e 5V and TA e 25 C

90 Timing and Load Diagrams

TLF9357 – 6

FIGURE 4 Transmit Timing - Start of Transmission

DP8391AV Datasheet(PDF) 7 Page - National Semiconductor (TI)

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