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DP8391AV Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP8391AV Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 12 page ![]() TLF9357 July 1993 DP8391ANS32491A SNI Serial Network Interface General Description The DP8391A Serial Network Interface (SNI) provides the Manchester data encoding and decoding functions for IEEE 8023 EthernetCheapernet type local area networks The SNI interfaces the DP8390 Network Interface Controller (NIC) to the Ethernet transceiver cable When transmitting the SNI converts non-return-to-zero (NRZ) data from the controller and clock pulses into Manchester encoding and sends the converted data differentially to the transceiver The opposite process occurs on the receive path where a digital phase-locked loop decodes 10 Mbits signals with as much as g18 ns of jitter The DP8391A SNI is a functionally complete Manchester encoderdecoder including ECL like balanced driver and re- ceivers on board crystal oscillator collision signal transla- tor and a diagnostic loopback circuit The SNI is part of a three chip set that implements the com- plete IEEE compatible network node electronics as shown below The other two chips are the DP8392 Coax Transceiv- er Interface (CTI) and the DP8390 Network Interface Con- troller (NIC) Incorporated into the CTI are the transceiver collision and jabber functions The Media Access Protocol and the buffer management tasks are performed by the NIC There is an isolation requirement on signal and power lines between the CTI and the SNI This is usually accomplished by using a set of miniature pulse transformers that come in a 16-pin plastic DIP for signal lines Power isolation however is done by using a DC to DC converter Features Y Compatible with Ethernet II IEEE 8023 10Base5 10Base2 and 10Base-T Y 10 Mbs Manchester encodingdecoding with receive clock recovery Y Patented digital phase locked loop (DPLL) decoder re- quires no precision external components Y Decodes Manchester data with up to g18 ns of jitter Y Loopback capability for diagnostics Y Externally selectable half or full step modes of opera- tion at transmit output Y Squelch circuits at the receive and collision inputs re- ject noise Y High voltage protection at transceiver interface (16V) Y TTLMOS compatible controller interface Y Connects directly to the transceiver (AUI) cable Table of Contents 10 System Diagram 20 Block Diagram 30 Functional Description 31 Oscillator 32 Encoder 33 Decoder 34 Collision Translator 35 Loopback 40 Connection Diagrams 50 Pin Descriptions 60 Absolute Maximum Ratings 70 Electrical Characteristics 80 Switching Characteristics 90 Timing and Load Diagrams 100 Physical Dimensions 10 System Diagram IEEE 8023 Compatible EthernetCheapernet Local Area Network Chip Set TLF9357 – 1 C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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