ADUC848BCP8-5 datasheet(88/108 Pages) AD

88 / 108 page

ADuC845/ADuC847/ADuC848

Rev. A | Page 88 of 108

As an alternative to providing two separate power supplies,

AVDD can be kept quiet by placing a small series resistor and/or

ferrite bead between it and DVDD, and then decoupling AVDD

separately to ground. An example of this configuration is shown

in Figure 65. In this configuration, other analog circuitry (such

as op amps and voltage reference) can be powered from the

AVDD supply line as well.

DVDD

AGND

AVDD

DGND

DIGITAL SUPPLY

–

BEAD

1.6

Ω

0.1

µF

0.1

µF

ADuC845/

ADuC847/

ADuC848

Figure 65. External Single-Supply Connections (56-Lead CSP Pin Numbering)

Notice that in both Figure 64 and Figure 65 a large value (10 µF)

reservoir capacitor sits on DVDD and a separate 10 µF capacitor

sits on AVDD. Also, local decoupling capacitors (0.1 µF) are

located at each VDD pin of the chip. As per standard design

practice, be sure to include all of these capacitors and ensure

that the smaller capacitors are closer than the 10 µF capacitors

to each VDD pin with lead lengths as short as possible. Connect

the ground terminal of each of these capacitors directly to the

underlying ground plane. Finally, note that, at all times, the

analog and digital ground pins on the part must be referenced

to the same system ground reference point. It is recommended

that the CSP paddle be soldered to ensure mechanical stability

but be floated with respect to system VDDs or grounds.

POWER-ON RESET OPERATION

An internal power-on reset (POR) is implemented on the

ADuC845/ADuC847/ADuC848. For DVDD below 2.63 V, the

internal POR holds the part in reset. As DVDD rises above 2.63 V,

an internal timer times out for typically 128 ms before the part

is released from reset. The user must ensure that the power

supply has at least reached a stable 2.7 V minimum level by this

time. Likewise on power-down, the internal POR holds the part

in reset until the power supply drops below 1 V. Figure 66

illustrates the operation of the internal POR.

128ms TYP

1.0V TYP

128ms TYP

2.63V TYP

1.0V TYP

INTERNAL

CORE RESET

DVDD

Figure 66. ADuC845/ADuC847/ADuC848 Internal Power-On Reset Operation

POWER CONSUMPTION

The DVDD power supply current consumption is specified in

normal and power-down modes. The AVDD power supply

current is specified with the analog peripherals disabled. The

normal mode power consumption represents the current drawn

from DVDD by the digital core. The other on-chip peripherals

(such as the watchdog timer and power supply monitor)

consume negligible current and are therefore included with the

normal operating current. The user must add any currents

sourced by the parallel and serial I/O pins, and those sourced by

the DAC to determine the total current needed at the ADuC845/

ADuC847/ADuC848 DVDD and AVDD supply pins. Also, current

drawn from the DVDD supply increases by approximately 5 mA

during Flash/EE erase and program cycles.

POWER-SAVING MODES

Setting the power-down mode bit, PCON.1, in the PCON SFR

described in Table 6, allows the chip to be switched from

normal mode into full power-down mode.

In power-down mode, both the PLL and the clock to the core

are stopped. The on-chip oscillator can be halted or can

continue to oscillate, depending on the state of the oscillator

power-down bit (OSC_PD) in the PLLCON SFR. The TIC,

driven directly from the oscillator, can also be enabled during

power-down. However, all other on-chip peripherals are shut

down. Port pins retain their logic levels in this mode, but the

DAC output goes to a high impedance state (three-state) while

ALE and PSEN outputs are held low. There are five ways to

terminate power-down mode:

•

Asserting the RESET Pin

Returns to normal mode. All registers are set to their reset

default value and program execution starts at the reset

vector once the RESET pin is de-asserted.

•

Cycling Power

All registers are set to their default state and program exe-

cution starts at the reset vector approximately 128 ms later.

•

Time Interval Counter (TIC) Interrupt

If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz

oscillator remains powered up even in power-down mode.

If the time interval counter (wake-up/RTC timer) is

enabled, a TIC interrupt wakes the part from power-down

mode. The CPU services the TIC interrupt. The RETI at

the end of the TIC ISR returns the core to the next

instruction after that one that enabled power-down.

ADUC848BCP8-5 Datasheet(PDF) 88 Page - Analog Devices

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