ADUC848BCP8-5 datasheet(25/108 Pages) AD

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ADuC845/ADuC847/ADuC848

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Power Control Register (PCON)

The PCON SFR contains bits for power-saving options and

general-purpose status flags as listed in Table 6.

SFR Address:

87H

Power-On Default:

00H

Bit Addressable:

Table 6. PCON SFR Bit Designations

Bit No.

Name

Description

SMOD

Double UART Baud Rate.

0 = Normal, 1 = Double Baud Rate.

SERIPD

Serial Power-Down Interrupt Enable. If this

bit is set, a serial interrupt from either SPI

or I2C can terminate the power-down

mode.

INT0PD

INT0 Power-Down Interrupt Enable.

If this bit is set, either a level (IT0 = 0) or a

negative-going transition (IT0 = 1) on the

INT0 pin terminates power-down mode.

ALEOFF

If set to 1, the ALE output is disabled.

GF1

General-Purpose Flag Bit.

GF0

General-Purpose Flag Bit.

Power-Down Mode Enable. If set to 1, the

part enters power-down mode.

-----

Not Implemented. Write Don’t Care.

ADuC845/ADuC847/ADuC848 Configuration Register

(CFG845/CFG847/CFG848)

The CFG845/CFG847/CFG848 SFR contains the bits necessary

to configure the internal XRAM and the extended SP. By default,

it configures the user into 8051 mode, that is, extended SP, and

the internal XRAM are disabled. When using in a program, use

the part name only, that is, CFG845, CFG847, or CFG848.

SFR Address:

AFH

Power-On Default:

00H

Bit Addressable:

Table 7. CFG845/CFG847/CFG848 SFR Bit Designations

Bit No.

Name

Description

EXSP

Extended SP Enable.

If this bit is set to 1, the stack rolls over

from SPH/SP = 00FFH to 0100H.

If this bit is cleared to 0, SPH SFR is

disabled and the stack rolls over from

SP = FFH to SP = 00H.

----

Not Implemented. Write Don’t Care.,

----

Not Implemented. Write Don’t Care.

----

Not Implemented. Write Don’t Care.

----

Not Implemented. Write Don’t Care.

----

Not Implemented. Write Don’t Care.

----

Not Implemented. Write Don’t Care.

XRAMEN

If this bit is set to 1, the internal XRAM is

mapped into the lower 2 kbytes of the

external address space.

If this bit is cleared to 0, the internal XRAM

is accessible and up to 16 MB of external

data memory become available. See

Figure 8.

ADUC848BCP8-5 Datasheet(PDF) 25 Page - Analog Devices

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