Electronic Components Datasheet Search
  English  ▼

X  

WM8962B Datasheet(PDF) 33 Page - Wolfson Microelectronics plc

Part # WM8962B
Description  Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
PDF  295 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8962B Datasheet(HTML) 33 Page - Wolfson Microelectronics plc

Back Button WM8962B Datasheet HTML 29Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 30Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 31Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 32Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 33Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 34Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 35Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 36Page - Wolfson Microelectronics plc WM8962B Datasheet HTML 37Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 33 / 295 page
background image
WM8962
Rev 4.3
33
POWER ON RESET TIMING
The WM8962 includes an internal Power-On-Reset (POR) circuit, which is used to reset the digital
logic into a default state after power up. The POR circuit is powered from AVDD and monitors
DCVDD. The internal POR
¯¯¯ signal is asserted low when AVDD and DCVDD are below minimum
thresholds.
A secondary reset circuit is associated with the PLLVDD supply. The PLLs are disabled and the
associated registers are undefined when PLLVDD is below its minimum threshold. Full device
functionality is not possible until AVDD, DCVDD and PLLVDD are above their respective reset
thresholds. The WM8962 can operate with PLLVDD tied to 0V, but the crystal oscillator, PLLs and
CLKOUT functions will not be supported.
The specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages.
Typical scenarios are illustrated in Figure 11 and Figure 12.
DCVDD
0V
0V
AVDD
0V
Vpora
Vpora_off
PLLVDD
LO
POR
Undefined
HI
Internal POR
Internal POR active
Internal POR active
Device Ready
(Full functionality)
Vpord_on
DCVDD
0V
0V
AVDD
0V
Vpora
Vpora_off
PLLVDD
LO
POR
Undefined
HI
Internal POR
Internal POR active
Internal POR active
Device Ready
(excluding PLL functions)
Vpord_on
Vporp_on
Full Functionality
Figure 11 Power On Reset Timing - AVDD Enabled First



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com