VT8501 Apollo MVP4

Revision 1.3 February 1, 2000

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Revision History

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Document Release

Date

Revision

Initials

0.1

Initial internal release based on Apollo MVP3 specification & Porsche HRM

GH

0.2

Updated/corrected signal list; added power signal detail, corrected misc features

GH

0.3

Added FP description, AC/DC tables, pin placement diagram; Fixed misc typos

GH

0.4

7/298

Reconciled with target spec: changed pinouts & poweron config, added registers

EC

0.5

7/27/98

Changed pinout; added pin descriptions; changed p/n to VT82C501; reformatted

DH

0.6

8/21/98

Changed pinouts TVD[0-2], TVHS, TVCLK per 7/30/98 rev 1.1 ballout

Changed PD[9-11,13-14,18-19], TVD[0-2,6-7], VIDCLK per 8/13, 1.3 ballout

Changed name of REQ4# / GNT4# to REQX# / GNTX# to match VT82C231

Added VGA and Graphics Accelerator registers

DH

0.7

8/24/98

Added remaining Graphics Engine registers

DH

0.8

9/11/98

Changed pinouts to match internal pinout document revision 1.5:

HCLK, MCLKI, MCLKO, GNDA, VCC2A, MD16-28, MD50-60

DH

0.9

10/15/98

Updated Feature Bullets

Changed pins F1, G1, G3, N2, and N4 to “Reserved, Do Not Connect”

Changed ADS#, M/IO#, W/R#, D/C#, BE[7-0]# to inputs, BRDY# to output

Added descriptions to VLF1 and VLF2 pins

Changed VSUS2 and VSUS3 to VSUS and corrected description

Changed VCC2 definition to 2.5V

Updated Register Definitions:

- Device 0 Rx68[1-0] changed; Rx78[5] & Rx88[0] reserved; Rx79 added

- Device 1 Rx41[1] reserved, Rx42[2] changed

- Default values added to 3D8, GR5, E-F, 20-22, 24-28, 2A, 2C, 2F, SR8-9, B-

12, 18-1B, 20-21, 24, 37-38, 96-99, 9E, BE, CE, and CR0-18, 1A-1C, 20, 21,

25, 27-2F, 34-3C, 52, 55, 56, 5E, 5F, 62, & 63

- CR11[6] reserved, CR17[4] extended function added, SRC[6] note added,

SRD[3].new reserved, SRD[7-4].new redefined, SR12[7-4, 3-0] redefined,

SR16-17 removed, CR1A-1C redefined, CR28/2C/2E deleted, CR2A[3-2]

reserved, CR62[3-0] redefined

Updated Functional Descriptions: corrected DFP config & deleted test modes

DH

0.91

10/21/98

Changed power / ground pin names to match design guide

Replaced ENPVDD (F1) and ENPVEE (G1) required for DFP interface

Moved CKE functions from MECC to RAS4-5#, SRASC#, SCASC#

Fixed error in numerical pin list AD15-AD18

Updated block diagram

DH

0.92

11/4/98

Changed part # to VT8501, changed VT82C686 to 686A & VT82C596 to 596A

Updated register definitions: Device 0 Rx51[4], 52[3,1], 53[3-0], 59-58[15-13],

MA Mapping Table, 69[7], 6B[3-1], 6C[7,3], 6D[4], 70[5,0], 73[4], 74[4-0],

76[3-0], 78[2], 79[7-0], 88[2], AC[6-4,0], AD, F0-FF, Device 1 Rx41[0],

42[3-2]; Fixed Device 1 bus #

DH

1.0

12/9/98

Fixed typographical error in pin lists: VCC3 pin # was W7, should be W21

DH

1.1

6/1/99

Fixed miscellaneous typographical errors and updated feature bullets

Changed defaults for Device 0 RxAC and RxAD

Changed device 0 Rx6[6], 52[3], 69[1] (VGA Ena Guard Bit), 79[1-0], FB[7]

Added missing device 1 registers Rx43, 44, and 47-46

DH

1.2

10/8/99

Fixed Bus 0 Device 1 Rx7-6[13-12] changed from WC to RO

Fixed Bus 1 Device 0 Rx3-0 Vendor & Device ID

DH

1.3

2/1/00

Added DSTN panel tables in intro/overview; added note to Device 0 Rx78[6]

Updated document logos; fixed ambient/case temp specs

DH