PCI4510PDV datasheet(42/220 Pages) TI

42 / 220 page

2−24

Table 2−17. IEEE 1394 Physical Layer Terminals

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

PDV

GHK

RGVF

I/O

DESCRIPTION

CNA

111

P17

P15

I/O

Cable not active. This terminal is asserted high when there are no ports receiving incoming

bias voltage. If it is not used, then this terminal must be strapped either to GND through a

resistor.

CPS

P10

M11

Cable power status input. This terminal is normally connected to cable power through a

400-k

Ω resistor. This circuit drives an internal comparator that is used to detect the presence

of cable power. If CPS is not used to detect cable power, then this terminal must be pulled to

AVDD.

FILTER0

FILTER1

105

106

T19

R17

T18

T19

I/O

PLL filter terminals. These terminals are connected to an external capacitance to form a

lag-lead filter required for stable operation of the internal frequency multiplier PLL running off

of the crystal oscillator. A 0.1-

µF ±10% capacitor is the only external component required to

complete this filter.

PC0

PC1

PC2

V10

W10

P09

R12

U13

V13

Power class programming inputs. On hardware reset, these inputs set the default value of the

power class indicated during self-ID. Programming is done by tying these terminals high or

low.

W13

V13

U18

U19

−

Current-setting resistor terminals. These terminals are connected to an external resistance

to set the internal operating currents and cable driver output currents. A resistance of

6.34 k

Ω ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.

TPA0P

TPA0N

V12

W12

V15

W15

I/O

Twisted-pair cable A differential signal terminals. Board trace lengths from each pair of

positive and negative differential signal pins must be matched and as short as possible to the

TPA1P

TPA1N

101

V15

W15

V18

W18

I/O

positive and negative differential signal pins must be matched and as short as possible to the

external load resistors and to the cable connector.

TPBIAS0

TPBIAS1

103

U12

U15

U17

I/O

Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper

operation of the twisted-pair cable drivers and receivers and for signaling to the remote nodes

that there is an active cable connection. Each of these pins must be decoupled with a 1.0-

µF

capacitor to ground.

TPB0P

TPB0N

V11

W11

V14

W14

I/O

Twisted-pair cable B differential signal terminals. Board trace lengths from each pair of

positive and negative differential signal pins must be matched and as short as possible to the

TPB1P

TPB1N

V14

W14

V16

W16

I/O

positive and negative differential signal pins must be matched and as short as possible to the

external load resistors and to the cable connector.

109

110

R18

R19

R18

R19

−

Crystal oscillator inputs. These pins connect to a 24.576-MHz parallel resonant fundamental

mode crystal. The optimum values for the external shunt capacitors are dependent on the

specifications of the crystal used (see Section 3.11.2, Crystal Selection). Terminal 5 has an

internal 10-k

Ω (nominal value) pulldown resistor. An external clock input can be connected

to the XI terminal. When using an external clock input, the XO terminal must be left

unconnected. Refer to Section 11.7 for the operating characteristics of the XI terminal.

PCI4510PDV Datasheet(PDF) 42 Page - Texas Instruments

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