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LM49321 Datasheet(PDF) 12 Page - Texas Instruments |
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LM49321 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 45 page ![]() Start Condition Stop Condition Data ACK SDA SCL TI2CSET TI2CHOLD TI2CSET TI2CSET ACK ACK Data ACK P S 6 - 0 7 - 1 0 7 - 1 0 W Host Address Start Condition SDA SCL Register Address Stop Condition LM49321, LM49321RLEVAL SNAS457C – SEPTEMBER 2008 – REVISED MAY 2013 www.ti.com TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0) Two Wire Mode Write Bus Transaction Two Wire Mode Write Bus Timing Figure 5. Two Wire Mode Write Bus When the part is configured as an I2C device then the LM49321 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the address input should be set to write to 1110000. Table 5. Chip Address A7 A6 A5 A4 A3 A2 A1 A0 Chip Address 0 EC EC 1 0 0 0 0 ADR = 0 0 0 0 1 0 0 0 0 ADR = 1 0 1 1 1 0 0 0 0 EC — Externally configured by ADR pin 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL |
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