DS1221

6 of 8

SECURITY OPTION

When activated by Dallas Semiconductor, the security option prevents unauthorized access. A sequence

of events must occur to gain access to the memories (Figure 3). First, a dummy read cycle or a 200 ns

active low reset pulse is executed to initialize the sequence. Second, a 64-bit access code must be

the data input/output signal (DQ). The code is written to the DS1221 without regard to the address.

Actual RAM locations are not written, as the security option is intercepting the data path until access is

granted. Instead, a special 64-bit write only register is written. Following the 64 write cycles, the register

is compared to a 64-bit pattern uniquely defined by the user and programmed into the DS1221 by Dallas

Semiconductor at the time of manufacture.

This pattern can only be interrogated by an intelligent

controller within the DS1221 and cannot be read by the user. If a read cycle occurs before 64 write cycles

are completed, the security sequence is aborted. When a correct match for 64 bits is received, the third

part of the security sequence begins by reading a 64-bit read only register. This register consists of 64 bits

also defined by the user and programmed into the DS1221 by Dallas Semiconductor at the time of

manufacture. For each of the 64 read cycles, 1 bit of the user-defined read only register is driven onto the

DQ line. This phase also requires that the 64 read cycles be consecutive. The data being read from the

read only register can be used by software to determine if the DS1221 will be permitted to be used with

that particular system. After the 64

subsequent memory cycles will be passed through and will become actual memory accesses based upon

must be executed again in order to access memory locations.

NOTE:

Contact Dallas Semiconductor sales office for code assignments.

SECURITY OPTION

AC ELECTRICAL CHARACTERISTICS

(0

°C to 70°C; V

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Read Cycle Time

250

ns

CE

Access Time

200

ns

RD

Access Time

100

ns

CE

to Output Low Z

10

ns

RD

to Output Low Z

10

ns

CE

to Output High Z

100

ns

RD

to Output High Z

100

ns

Read Recovery

50

ns

Write Cycle

250

ns

Write Pulse Width

170

ns

Write Recovery

50

ns

Data Setup

100

ns

Data Hold Time

0ns

CE

Pulse Width

170

ns

Reset Pulse Width

200

ns