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LM64 Datasheet(PDF) 22 Page - Texas Instruments |
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LM64 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 38 page  LM64 SNAS207A – MAY 2004 – REVISED MARCH 2013 www.ti.com LM64 REGISTER DESCRIPTIONS IN FUNCTIONAL ORDER Fan Control Registers Address Read/ Bit POR Name Description Hex Write s Value 4AHEX PWM AND RPM REGISTER 7:6 00 These bits are unused and always set to 0. 0: the PWM Value (register 4C) and the Lookup Table (50–5F) are read-only. The PWM value (0 to 100%) is determined by the current remote diode temperature and PWM the Lookup Table, and can be read from the PWM value register. Program 5 1 1: the PWM value (register 4C) and the Lookup Table (Register 50–5F) are read/write enabled. Writing the PWM Value register will set the PWM output. This is also the state during which the Lookup Table can be written. PWM 0: the PWM output pin will be 0 V for fan OFF and open for fan ON. 4 0 Output 1: the PWM output pin will be open for fan OFF and 0 V for fan ON. Polarity PWM Clock if 0, the master PWM clock is 360 kHz 4A R/W 3 0 Select if 1, the master PWM clock is 1.4 kHz. 2 0 [Reserved] Always write 0 to this bit. 00: Traditional tach input monitor, false readings when under minimum detectable RPM. 01: Traditional tach input monitor, FFFF reading when under minimum detectable RPM. Tachometer 1:0 00 10: Most accurate readings, FFFF reading when under minimum detectable RPM. Mode 11: Least effort on programmed PWM of fan, FFFF reading when under minimum detectable RPM. Note: If the PWM Clock is 360 kHz, mode 00 is used regardless of the setting of these two bits. 4BHEX FAN SPIN-UP CONFIGURATION REGISTER 7:6 0 These bits are unused and always set to 0 If 0, the fan spin-up uses the duty cycle and spin-up time, bits 0–4. If 1, the LM64 sets the PWM output to 100% until the spin-up times out (per bits 0–2) Fast or the minimum desired RPM has been reached (per the Tachometer Setpoint Tachometer 5 1 setting) using the tachometer input, whichever happens first. This bit overrides the Spin-Up PWM Spin-Up Duty Cycle register (bits 4:3)—PWM output is always 100%. If PWM Spin-Up Time (bits 2:0) = 000, the Spin-Up cycle is bypassed, regardless of the state of this bit. 00: Spin-Up cycle bypassed (no Spin-Up), unless Fast Tachometer Terminated Spin- PWM Up (bit 5) is set. 4B R/W 4:3 11 Spin-Up 01: 50% Duty Cycle 10: 75%–81% Depends on PWM Frequency. See Applications Notes. 11: 100% 000: Spin-Up cycle bypassed (No Spin-Up) 001: 0.05 seconds 010: 0.1 s PWM 011: 0.2 s 2:0 111 Spin-Up 100: 0.4 s Time 101: 0.8 s 110: 1.6 s 111: 3.2 s 4DHEX FAN PWM FREQUENCY REGISTER 7:5 000 These bits are unused and always set to 0 PWM The PWM Frequency = PWM_Clock / 2n, where PWM_Clock = 360 kHz or 1.4 kHz 4D R/W Frequency 4:0 10111 (per the PWM Clock Select bit in Register 4A), and n = value of the register. Note: n = 0 is mapped to n = 1. See the Applications Notes at the end of this datasheet. 22 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM64 |
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