TIBPAL22V10AC datasheet(12/20 Pages) TI1

12 / 20 page

TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM

HIGH-PERFORMANCE

IMPACT ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS024A − OCTOBER 1986 − REVISED APRIL 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

preload procedure for registered outputs (see Notes 2 and 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be

tested without having to step through the entire state-machine sequence. Each register is preloaded individually

by following the steps given below:

Step 1. With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH.

Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.

Step 3. Pulse pin 1, clocking in preload data.

Step 4. Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level

at the output pin.

tsu

VIHH

VIL

VOL

VOH

VIH

Pin 13

Pin 1

Registered I/O

Input

Output

VIH

VIL

Figure 2. Preload Waveforms

NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed

accordingly.

td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.

TIBPAL22V10AM is Not Recommended For New Designs

TIBPAL22V10AC Datasheet(PDF) 12 Page - Texas Instruments