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OUTPUT MODE OF OPERATION—DC-COUPLED

DAC/Encoder

(DaVinci

TM

)

CVBS

Y’

C’

75 W

Y’

OUT

75 W

C’

OUT

75 W

+1.8V

75 W

75 W

SDTV

CVBS

S-Video Y’

S-VideoC’

480i/576i

Y’P’ P’

G’B’R’

B

R

75 W

S-Video

500 W

500 W

500 W

5

8

7

6

1

2

3

4

V

S+

GND

CH.2IN

CH.3IN

CH.1IN

CH.3OUT

CH.2OUT

CH.1OUT

THS7315

CVBS

OUT

+

+3.3V

22 F

m

0.1 F

m

Gain=

5.2V/V

THS7315

SLOS532 – JUNE 2007

APPLICATION INFORMATION (continued)

One other issue that must be taken into account is the dc-bias point. The dc-bias point is a function of the power

supply. As such, there is as a low-pass filter. Additionally, the time to charge the capacitor to the final dc bias

point is also a function of the pull-up resistor and the input capacitor. Lastly, the input capacitor forms a

high-pass filter with the parallel impedance of the pull-up resistor and the 800-k

Ω resistor. Generally, it is good to

A 0.1-

μF input capacitor with a 9.31-M

Ω pull-up resistor equals about a 2.2-Hz high-pass corner frequency.

signals.

The THS7315 incorporates a rail-to-rail output stage that can be utilized to drive the line directly without the

need for large ac-coupling capacitors, as shown in Figure 8. This architecture offers the best line tilt and field tilt

(or droop) performance because no ac coupling occurs. Keep in mind that if the input is ac-coupled, then the

resulting tilt arising from the input ac coupling is still seen on the output, regardless of the output coupling. The

80-mA output current drive capability of the THS7315 was designed to drive two video lines per channel

simultaneously—essentially, a 75-

Ω load—while keeping the output dynamic range as wide as possible.

Figure 8. Typical SDTV CVBS/Y'/C' System with DC-Coupled Line Driving

One concern about dc coupling arises when the line is terminated to ground. If the ac-bias input configuration is

used, the THS7315 output has a dc bias on the output. With two lines terminated to ground, this configuration

creates a dc current path, resulting in a slightly decreased high output voltage swing as well as an increase in

device power dissipation. While the THS7315 was designed to operate with junction temperatures of up to

+125

°C, care must be taken to ensure that the junction temperature does not exceed this level; otherwise,

long-term reliability could suffer. Although this configuration only adds less than 10 mW of power dissipation per

channel, the overall low power dissipation of the THS7315 design minimizes potential thermal issues even when

using the SOIC package at high ambient temperatures.

Note that the THS7315 can drive the line with dc coupling regardless of the input mode of operation. The only

requirement is to verify that the video line has proper termination in series with the output (typically 75

Ω). This

termination also helps isolate capacitive loading effects from the THS7315 output. Failure to isolate capacitive

loads may result in instabilities with the output buffer, potentially causing ringing or oscillating to appear. The

stray capacitance appearing directly at the THS7315 output pins should be kept below 25 pF.

13

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