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CS5516-ASZ Datasheet(PDF) 9 Page - Cirrus Logic

Part # CS5516-ASZ
Description  16BIT/20-BIT BRIDGE TRANSDUCER A/D CONVERTER
PDF  41 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5516-ASZ Datasheet(HTML) 9 Page - Cirrus Logic

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SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 5%;
VA-, VD- = -5V
±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)
Parameter
Symbol
Min
Typ
Max
Units
Master Clock Frequency: Internal Oscillator / External Clock
XIN
1.0
4.096
5.0
MHz
Master Clock Duty Cycle
40
-
60
%
Rise Times
Any Digital Input
(Note 18)
Any Digital Output
trise
-
-
-
50
1.0
-
µs
ns
Fall Times
Any Digital Input
(Note 18)
Any Digital Output
tfall
-
-
-
50
1.0
-
µs
ns
Startup
Power-on Reset Period
tpor
-
100
-
ms
Oscillator Start-up Time
XTAL = 4.9152 MHz(Note 19)
tost
-60
-
ms
RST Pulse Width
tres
1/XIN
-
-
ns
Serial Port Timing
Serial Clock Frequency
SCLK
-
-
2.4
MHz
Serial Clock
Pulse Width High
Pulse Width Low
t1
t2
200
200
-
-
-
-
ns
ns
SID Write Timing
CS Enable to Valid Latch Clock
t3
150
-
-
ns
Data Set-up Time prior to SCLK rising
t4
50
-
-
ns
Data Hold Time After SCLK Rising
t5
50
-
-
ns
SCLK Falling Prior to CS Disable
t6
50
-
-
ns
SOD Read Timing
CS to Data Valid
t7
-
-
150
ns
SCLK Falling to New Data Bit
t8
-
-
170
ns
SCLK Falling to SOD Hi-Z
t9
-
-
200
ns
DRDY Falling to Valid Data
(CS = 0)
t10
-
-
150
ns
CS Rising to SOD Hi-Z
t11
-
-
150
ns
CS Disable Hold Time
t12
50
-
-
ns
CS Enable Set-up Time
t13
150
-
-
ns
CS Enable Hold Time
t14
50
-
-
ns
CS Disable Set-up Time
t15
150
-
-
ns
Notes: 18. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
19. Oscillator start-up time varies with crystal parameters. This specification does not apply when using
an external clock source.
CS5516, CS5520
DS74F1
9
DS74F2
9



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