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CS5516-ASZ Datasheet(PDF) 18 Page - Cirrus Logic

Part # CS5516-ASZ
Description  16BIT/20-BIT BRIDGE TRANSDUCER A/D CONVERTER
PDF  41 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5516-ASZ Datasheet(HTML) 18 Page - Cirrus Logic

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AIN and VREF Non-Ratiometric Offset Registers
MSB
LSB
Register
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
Reset (R)
000000
000
0
0
0
One LSB represents 2
-23 proportion of the internal MDRV (≈2.5 Volts)
DAC Register
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
Register
DAC3
DAC2
DAC1
DAC0
EXC
F1
F0
D16
G1
G0
U/B
D12
Reset (R)
000000000000
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register
A/S
EC
D9
D8
CC3
CC2
CC1
CC0
D3
D2
D1
RF
Reset (R)
000000000000
BIT
NAME
VALUE
FUNCTION
DAC3
DAC Sign Bit
0
1
R
1
Add Offset
Subtract Offset
DAC2-0
DAC Bits
000
001
010
011
100
101
110
111
R
25% Offset
50% Offset
75% Offset
100% Offset
125% Offset
150% Offset
175% Offset
Bits
D19 to D0
0
R
These bits mirror the
read only
2
Configuration Register
Note: 1. Reset State
2. A write to these bits does not change the register bit values.
AIN Ratiometric Offset Register
MSB
LSB
Register
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
Reset (R)
000000
000
0
0
0
One LSB represents 2
-23 proportion of the voltage [<(VREF+) - (VREF-)>/GAIN] where GAIN = 25 X PGA Gain
GAIN Register
MSB
LSB
Register
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
Reset (R)
100000
000
0
0
0
The gain register span from 0 to (2-2
-23). After Reset the MSB=1, all other bits are 0.
Table 4. Calibration Registers
CS5516, CS5520
18
DS74F1
18
DS74F2



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