CS5516-ASZ datasheet(23/41 Pages) CIRRUS

23 / 41 page

quencies are possible but may introduce a jitter

component in the BX output signals. It is de-

sirable not to choose an excitation frequency

where interference components are present,

such as 50 Hz or 60 Hz or their harmonics. The

XIN frequency can be divided down using a

counter IC external to the A/D converter. Fexc

would be input to the BX1 pin of the converter

to synchronize the internal operations of the am-

plifiers and synchronous detection circuitry and

to generate a clock output from the BX2 pin.

The BX2 output is then used to drive the bridge

amplifier with a signal of proper phase for detec-

tion by the converter.

Figure 8 indicates the

necessary phase of the signals to ensure proper

demodulation.

Whenever the dynamic excitation clock output

from either the BX1 and BX2 pins (during inter-

nal excitation) or from the BX2 pin (during

external excitation) changes states, the converter

waits 64 XIN cycles before sampling the AIN

and VREF signal inputs. The delay allows some

time for the signal to settle from the modulation

event.

Input Filtering

Some load cells are located a distance from the

input to the converter. Under these conditions,

separate twisted pair cabling is recommended for

the excitation drive to the bridge, the excitation

sense leads (if used), and for the AIN

±/ΑΙΝ−

signal leads. If the AIN+/AIN- leads to the con-

verter and the VREF+/VREF- leads to the con-

verter are filtered, care should be exercised in

the choice of components. With either dc or ac

excitation, one should limit any input filtering

resistors on AIN to below 1 k

Ω. Values greater

than this will degrade noise performance of the

converter. In ac excitation applications, any fil-

tering must be broadband enough that the

switched dc excitation signal can settle within 10

µsecs. Failure to meet this settling requirement

will affect measurement accuracy. Figure 9 illus-

trates acceptable filter components for ac

excitation. If only differential filtering is re-

quired, a single capacitor can be placed between

AIN+ and AIN- (and VREF+ and VREF-) in

place of two capacitors to ground.

Voltage Reference Considerations

The CS5516/20 include an on-chip voltage refer-

ence which is output on the MDRV- and

referenced from the MDRV+ pin. The converter

is designed to be operated as a ratiometric meas-

urement device. The 2-channel delta-sigma

converter uses the internal MDVR (Modulator

Differential Voltage Reference) as its reference.

Since the MDVR is used for converting both the

AIN and VREF signals at the same time, the ab-

solute value of the MDVR and its tempco are

not important when the CS5516/20 is used in the

ratiometric measurement mode. The voltage ref-

erence output, MDVR-, should be decoupled

using a 1

µF capacitor which is connected to the

MDRV+ supply line. Voltage reference decou-

BX1 (In)

BX2 (Out)

Demod Clock

(Internal)

t dd

Note: The signals from the bridge into AIN+ and

VREF+ of the converter must be in phase

with the demodulation clock.

≤ 64/XIN

Figure 8. External Excitation Clock Phasing

CS5516

CS5520

VREF+

VREF-

AIN+

AIN-

470 pF

7.5k

EXC+

EXC-

0.0047

µF

0.0047

µF

300

AIN+

AIN-

Figure 9. AIN and VREF Input Filter Components

CS5516, CS5520

DS74F1

DS74F2

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