DS21448 datasheet(39/60 Pages) DALLAS

39 / 60 page

DS21448 3.3V T1/E1/J1 Quad Line Interface

39 of 60

Figure 7-4. Dual Connector-Protected Interface Using Receive Termination

VDD

VSS

TTIP

TRING

RTIP

RRING

Dallas

Semiconductor

DS21448

VDD

VSS

0.01

0.1

1.0

MCLK

2.048MHz (THIS CAN ALSO

BE 1.544MHz FOR T1 ONLY

OPERATION)

0.1

FUSE

BALANCED LINE

(100

W/120W)

UNBALANCED

LINE (75

FUSE

0.22

FUSE

0.22

0.8:1:1CT

51.1

BALANCED LINE

(100

W/120W)

UNBALANCED

LINE (75

1:1

0.8:1

1.6:1

2:1

0.8:1:1CT

NOTE 1:

REFER TO APPLICATION NOTE 384 FOR A COMPLETE DISCUSSION OF THIS CIRCUIT.

NOTE 2:

ALL RESISTOR VALUES ARE ±1%.

NOTE 3:

THE FUSES ARE OPTIONAL TO PREVENT AC POWER LINE CROSSES FROM COMPROMISING THE TRANSFORMERS.

NOTE 4:

S IS A SIDACTOR.

NOTE 5:

THE RT RESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS (Table 7-C). NO RETURN LOSS IS REQUIRED

FOR T1 APPLICATIONS.

NOTE 6:

THE 68

mF IS USED TO KEEP THE LOCAL POWER PLANE POTENTIAL WITHIN TOLERANCE DURING A SURGE.

DS21448 Datasheet(PDF) 39 Page - Dallas Semiconductor

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