12-Bit Write

Command

Decoder

MSB

Write

Command

Bit 11

36 Bits

36

---

47

LSB

0

---

11

12

24

35

36 Bits

12 Bits

Write Command = 3AAh (001110101010b)

GS Data

Latch Pulse

(Internal)

Write

Command

Bit 0

---

23

LSB

OUT0

GS Data

Bit 11

0

---

11

12

24

---

35

---

23

OUT0

GS Data

Bit 0

OUT1

GS Data

Bit 11

OUT1

GS Data

Bit 0

OUT2

GS Data

Bit 11

OUT2

GS Data

Bit 0

---

OUT0

GS Data

Bit 11

OUT0

GS Data

Bit 0

OUT1

GS Data

Bit 11

OUT1

GS Data

Bit 0

OUT2

GS Data

Bit 11

OUT2

GS Data

Bit 0

MSB

The internal latch pulse is generated after 8 t

without SDI clocking.

CYCLES

Shift Data (Internal)

Shift Clock (Internal)

48-Bit Shift Register

36-Bit GS Data Latch

To Grayscale Timing

Control Circuit

TLC5973

www.ti.com

SBVS225B – MARCH 2013 – REVISED MAY 2014

8.6 Register Maps

8.6.1 Register and Data Latch Configuration

The TLC5973 has a 48-bit shift register and a 36-bit data latch that stores GS data. When the internal GS data

latch pulse is generated and the data of the 12 MSBs in the shift register are 3AAh, the lower 36-bit data in the

48-bit shift register are copied into the 36-bit GS data latch. If the data of the 12 MSBs is not 3AAh, the 36-bit

data are not copied into the 36-bit GS data latch. Figure 21 shows the shift register and GS data latch

configurations. Table 3 shows the 48-bit shift register bit assignment.

Figure 21. Common Shift Register and Control Data Latches Configuration

Table 3. 48-Bit Shift Register Data Bit Assignment

BITS

BIT NAME

CONTROLLED CHANNEL/FUNCTIONS

0 to 11

GSOUT2

GS data bits 0 to 11 for OUT2

12 to 23

GSOUT1

GS data bits 0 to 11 for OUT1

24 to 35

GSOUT0

GS data bits 0 to 11 for OUT0

Data write command (3AAh) for GS data.

The lower 36-bit GS data in the 48-bit shift register are copied to the GS data latch

36 to 47

WRTCMD

when the internal GS latch is generated (when these data bits are 3AAh,

001110101010b).

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