TLC5973DR datasheet(9/34 Pages) TI1

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fCLK(SDI)

SDI

SDO

OUT0

OFF

)

OUTnH

)

OUTnL

OUT1

OUT2

VCC

Data Transfer

Period Memory

(Internal in 1st Device)

1st Device

1st Data (0)

fCLK(SDI)

Data transfer period (t

CYCLE) is stored.

tSDI

tWL

tWH

OUTEN Signal

(Internal)

Low = SDI data are not output from SDO.

SCLK Signal

(Internal in 1st Device)

48-Bit Shift Register MSB

(Internal in 1st Device)

48-Bit Shift Register MSB-1

(Internal in 1st Device)

48-Bit Shift Register LSB+1

(Internal in 1st Device)

Recognized Data,

SIN Signal

(Internal in 1st Device)

48-Bit Shift Register LSB

(Internal in 1st Device)

GSLAT Signal

(Internal in 1st Device)

New GS Data

(All GS data are ‘0’ when VCC powers up.)

Data transfer period (t

CYCLE) is stored.

2nd

Data (0)

3rd

Data (1)

4th

Data (1)

5th

Data (1)

48th

Data (0)

2nd Device

1st Data (0)

2nd

Data (0)

48th

Data (0)

1st Device

1st Data (0)

47th

Data

48th Data (0)

4th Data (1)

3rd Data (1)

2nd Data (0)

5th Data (1)

1st Data (0)

4th Data (1)

3rd Data (1)

2nd Data (0)

5th Data (1)

4th Data (1)

1st Data (0)

3rd Data (1)

2nd Data (0)

1st Data (0)

48th Data (0)

3rd Data (0)

2nd Data (0)

(1)

SCLK Signal

(Internal in 2nd Device)

48th Data (0)

47th

Data

47th Data

2nd Data (0)

1st Data (0)

46th

Data

High = SDI data are output from SDO.

1st Data (0)

(All GS data are ‘0’ when VCC powers up.)

47th Data (0)

48th Data (0)

New GS Data

36-Bit GS Data Latch

(Internal in 1st Device)

GS Data Latch

(Internal in 2nd Device)

GSLAT Signal

(Internal in 2nd Device)

48-Bit Shift Register LSB

(Internal in 2nd Device)

(for EOS)

(for GSLAT)

48th Data (0)

TLC5973

www.ti.com

SBVS225B – MARCH 2013 – REVISED MAY 2014

Timing Diagrams (continued)

(1) OUTn on-time changes, depending on the data in the 36-bit GS data latch.

Figure 11. Data Write and OUTn Switching Timing

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