TLK1201RCP, TLK1201IRCP

ETHERNET TRANSCEIVERS

SLLS506E − AUGUST 2001 − REVISED MAY 2007

3

POST OFFICE BOX 655303

block diagram

2:1

MUX

PRBS

Generator

10 Bit

Registers

TD(0−9)

PRBSEN

LOOPEN

Parallel to

Serial

Phase Generator

Clock

REFCLK

Control

Logic

MODESEL

ENABLE

TESTEN

Interpolator

and

Clock Extraction

PRBS

Verification

Serial to Parallel

and

Comma Detect

Clock

RBC1

RBC0

SYNC/PASS

RD(0−9)

SYNCEN

RBCMODE

JTAG

Control

Register

JTMS

JTRSTN

JTDI

TCK

JTDO

2:1

MUX

2:1

MUX

Clock

Data

TXP

TXN

RXP

RXN

LOS

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

SIGNAL

MODESEL

15

I

Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When

low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default

mode is the TBI.

LOS

26

O

Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.

If magnitude of RXP−RXN > 150 mV, LOS = 1, valid input signal

If magnitude of RXP−RXN < 150 mV and > 50 mV, LOS is undefined

If magnitude of RXP−RXN < 50 mV, LOS = 0, loss of signal

RBCMODE

32

I

Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on

RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on

RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is

output on RBC0 and RBC1 is held low.