THS3091 datasheet(23/31 Pages) TI

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DIE

Side View (a)

DIE

End View (b)

Thermal

Pad

Bottom View (c)

PowerPAD™ DESIGN CONSIDERATIONS

0.140

0.060

0.010

vias

Top View

0.035

0.080

0.050

0.176

0.030

0.026

0.010

0.035

0.100

0.300

Pin 1

All Units in Inches

THS3091

THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

through onboard transmission lines. For short

in the lead frame being exposed as a thermal pad on

connections, consider the trace and the input to

the underside of the package [see Figure 71(c)].

the next device as a lumped capacitive load.

Because this thermal pad has direct thermal contact

Relatively wide traces (50 mils to 100 mils)

with the die, excellent thermal performance can be

should be used, preferably with ground and

achieved by providing a good thermal path away from

power planes opened up around them. Estimate

the thermal pad. Note that devices such as the

the total capacitive load and determine if isolation

THS3091/5 have no electrical connection between

resistors on the outputs are necessary. Low

the PowerPAD and the die.

parasitic capacitive loads (< 4 pF) may not need

The PowerPAD package allows for both assembly

an RS because the THS3091/5 are nominally

and thermal management in one manufacturing oper-

compensated to operate with a 2-pF parasitic

ation. During the surface-mount solder operation

load. Higher parasitic capacitive loads without an

(when the leads are being soldered), the thermal pad

RS are allowed as the signal gain increases

can also be soldered to a copper area underneath the

(increasing the unloaded phase margin). If a long

package. Through the use of thermal paths within this

trace is required, and the 6-dB signal loss intrin-

copper area, heat can be conducted away from the

sic to a doubly terminated transmission line is

package

into

either

ground

plane

other

acceptable, implement a matched impedance

heat-dissipating device.

transmission line using microstrip or stripline

techniques (consult an ECL design handbook for

The PowerPAD package represents a breakthrough

microstrip and stripline layout techniques). A

in combining the small area and ease of assembly of

50-

Ω environment is not necessary onboard, and

surface

mount

with

the,

heretofore,

awkward

fact,

higher

impedance

environment

mechanical methods of heatsinking.

improves distortion as shown in the distortion

versus load plots. With a characteristic board

trace impedance based on board material and

trace dimensions, a matching series resistor into

the trace from the output of the THS3091/5 is

used as well as a terminating shunt resistor at the

input of the destination device. Remember also

that the terminating impedance is the parallel

combination of the shunt resistor and the input

Figure 71. Views of Thermal Enhanced Package

impedance of the destination device; this total

effective impedance should be set to match the

Although there are many ways to properly heatsink

trace impedance. If the 6-dB attenuation of a

the PowerPAD package, the following steps illustrate

doubly terminated transmission line is unaccept-

the recommended approach.

able, a long trace can be series-terminated at the

source end only. Treat the trace as a capacitive

load in this case. This does not preserve signal

integrity as well as a doubly terminated line. If the

input impedance of the destination device is low,

there is some signal attenuation due to the

voltage divider formed by the series output into

the terminating impedance.

•

Socketing a high-speed part like the THS3091/5

is not recommended. The additional lead length

and pin-to-pin capacitance introduced by the

socket can create an extremely troublesome

parasitic network which can make it almost im-

possible to achieve a smooth, stable frequency

response. Best results are obtained by soldering

the THS3091/5 parts directly onto the board.

The

THS3091/5

are

available

Figure 72. DDA PowerPAD PCB Etch and Via

thermally-enhanced PowerPAD family of packages.

Pattern

These packages are constructed using a downset

leadframe on which the die is mounted [see Fig-

ure 71(a) and Figure 71(b)]. This arrangement results

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