TMS320DM6435 datasheet(89/252 Pages) TI1

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TMS320DM6435

Digital Media Processor

www.ti.com

SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-19. PINMUX0 Register Description (continued)

Bit

Field Name

Description

Pins Controlled

Chip Select 4 Select.

Sub-Block 1

00 = GPIO pin (GP32) (default)

EM_CS4/GP[32]

9:8

CS4SEL

01 = EMIFA Chip Select 4 (EM_CS4)

The PINMUX0 field CS4SEL alone controls the

10 = Reserved

muxing of this pin.

11 = Reserved

Chip Select 5 Select.

Sub-Block 1

00 = GPIO pin (GP33) (default)

EM_CS5/GP[33]

7:6

CS5SEL

01 = EMIFA Chip Select 5 (EM_CS5)

The PINMUX0 field CS5SEL alone controls the

10 = Reserved

muxing of this pin.

11 = Reserved

Reserved. For proper device operation, the user should only write "0" to these bits

5:3

RESERVED

(default).

Sub-Block 0

C_WE/EM_R/W/GP[35]

C_FIELD/EM_A[21]/GP[34]

CI7(CCD15)/EM_A[13]/GP[51]

CI6(CCD14)/EM_A[14]/GP[50]

CI5(CCD13)/EM_A[15]/GP[49]

CI4(CCD12)/EM_A[16]/GP[48]

CI3(CCD11)/EM_A[17]/GP[47]

CI2(CCD10)/EM_A[18]/GP[46]

CI1(CCD9)/EM_A[19]/GP[45]

CI0(CCD8)/EM_A[20]/GP[44]

EMIFA Pinout Modes

Sub-Block 1

This field does not affect the actual EMIFA operation. It only determines what

multiplexed pins in the EMIFA/VPSS Block serves as EMIFA pins.

EM_D[7]/GP[21]

EM_D[6]/GP[20]

000b = No EMIFA Mode.

EM_D[5]/GP[19]

None of the multiplexed pins in the EMIFA/VPSS Block serves as EMIFA pins.

EM_D[4]/GP[18]

EM_D[3]/GP[17]

001b = 8-bit EMIFA (Async) Pinout Mode 1.

EM_D[2]/GP[16]

(Up to 16M-Byte address reach per Chip Select Space).

EM_D[1]/GP[15]

Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit

EM_D[0]/GP[14]

EMIFA (Async or NAND) + 16-bit CCDC (VPFE)

2:0

AEM(1)

EM_CS2/GP[12]

EM_A[3]/GP[11]

010b = Reserved.

EM_A[4]/GP[10]/(AEAW2/PLLMS2)

011b = Reserved.

EM_A[1]/(ALE)/GP[9]/(AEAW1/PLLMS1)

EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0)

100b = Reserved.

EM_A[0]/GP[7]/(AEM2)

EM_BA[0]/GP[6]/(AEM1)

101b = 8-bit EMIFA (NAND) Pinout Mode 5.

EM_BA[1]/GP[5]/(AEM0)

Pinout allows up to a maximum of these functions from EMIFA/VPSS Block: 8-bit

EMIFA (NAND) + 16-bit CCDC (VPFE)

Sub-Block3

110b through 111b = Reserved.

EM_A[12]/GP[89]

EM_A[11]/GP[90]

EM_A[10]/GP[91]

EM_A[9]/GP[92]

EM_A[8]/GP[93]

EM_A[7]/GP[94]

EM_A[6]/GP[95]

EM_A[5]/GP[96]

The pin mux for these pins are controlled by a

combination of AEM and other PINMUX0 fields,

including CWENSEL, CFLDSEL, AEAW,

CI76SEL, CI54SEL, CI32SEL, and CI10SEL. (2)

(1)

The AEM default value is latched at reset from AEM[2:0] configuration inputs. The latched values are also shown at BOOTCFG.DAEM

(read-only).

(2)

For the full set of valid configurations of these pins, see Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary.

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