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TMS320VC5510 Datasheet(PDF) 53 Page - Texas Instruments

Part # TMS320VC5510
Description  Fixed-Point Digital Signal Processors
PDF  90 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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TMS320VC5510 Datasheet(HTML) 53 Page - Texas Instruments

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Electrical Specifications
53
June 2000 − Revised September 2007
SPRS076O
5.6
Clock Options
This section provides the timing requirements and switching characteristics for the various clock options
available on the 5510/5510A.
5.6.1 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of one, two, or four
to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock mode
register. The contents of this field only affect clock generation while the device is in bypass mode. In this mode,
the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5−1 and Table 5−2 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5−2).
Table 5−1. CLKIN in Bypass Mode Timing Requirements
NO.
VC5510/5510A-160
VC5510/5510A-200
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
C7
tc(CI)
Cycle time, CLKIN
20
†
20
†
ns
C8
tf(CI)
Fall time, CLKIN
6
6
ns
C9
tr(CI)
Rise time, CLKIN
6
6
ns
C10
tw(CIL)
Pulse duration, CLKIN low
4
4
ns
C11
tw(CIH) Pulse duration, CLKIN high
4
4
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
Table 5−2. CLKOUT in Bypass Mode Switching Characteristics
NO.
PARAMETER
VC5510/5510A-160
VC5510/5510A-200
UNIT
NO.
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
C1
tc(CO)
Cycle time, CLKOUT
20
tc(CI)/N‡
20
tc(CI)/N‡
ns
C2
td(CI-CO)
Delay time, CLKIN high/low to CLKOUT high/low
1
7
14
1
7
14
ns
C3
tf(CO)
Fall time, CLKOUT
1
1
ns
C4
tr(CO)
Rise time, CLKOUT
1
1
ns
C5
tw(COL)
Pulse duration, CLKOUT low
H−1
H+1
H−1
H+1
ns
C6
tw(COH)
Pulse duration, CLKOUT high
H−1
H+1
H−1
H+1
ns
‡ N = Clock frequency synthesis factor
C4
C3
CLKOUT
CLKIN
C5
C2
C8
C9
C1
C7
C6
C11
C10
NOTE A: The relationship of CLKIN to CLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 5−2 is intended
to illustrate the timing parameters only and may differ based on configuration.
Figure 5−2. Bypass Mode Clock Timing



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