AD7490 datasheet(10/24 Pages) AD

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–10–

AD7490

REV. A

Table II. Channel Selection

Analog Input

ADD3

ADD2

ADD1

ADD0

Channel

0000VIN0

0001VIN1

0010VIN2

0011VIN3

0100VIN4

0101VIN5

0110VIN6

0111VIN7

1000VIN8

1001VIN9

1010VIN10

1011VIN11

1100VIN12

1101VIN13

1110VIN14

1111VIN15

Table III. Power Mode Selection

PM1

PM0

Mode

Normal Operation

In this mode, the AD7490 remains in full

power mode regardless of the status of any of

the logic inputs. This mode allows the fastest

possible throughput rate from the AD7490.

Full Shutdown

In this mode, the AD7490 is in full shut-down

mode, with all circuitry on the AD7490 powering

down. The AD7490 retains the information

in the Control Register while in full shutdown.

The part remains in full shutdown until these

bits are changed in the Control Register.

Auto Shutdown

In this mode, the AD7490 automatically enters

shutdown mode at the end of each conversion

when the Control Register is updated. Wake-up

time from shutdown is 1

µs and the user should

ensure that 1

µs has elapsed before attempting

to perform a valid conversion on the part in

this mode.

Auto Standby

In this standby mode, portions of the AD7490

are powered down, but the on-chip bias gen-

erator remains powered-up. This mode is

similar to Auto Shutdown and allows the part

to power-up within one dummy cycle, i.e.,

µs with a 20 MHz SCLK.

For more information, see the Modes of Operation section.

SEQUENCER OPERATION

The configuration of the SEQ and Shadow Bits in the Control

of the sequencer function. Table IV outlines the four modes of

operation of the Sequencer.

Table IV. Sequence Selection

SEQ

SHADOW

Sequence Type

This configuration means the sequence

function is not used. The analog input

channel selected for each individual

conversion is determined by the contents

of the channel address bits ADD0

through ADD3 in each prior write

operation. This mode of operation reflects

the normal operation of a multichannel

ADC, without sequencer function being

used, where each write to the AD7490

selects the next channel for conversion.

(See Figure 2.)

This configuration selects the Shadow

to the Control Register, the following

write operation will load the contents

of the Shadow Register. This will program

the sequence of channels to be converted

on continuously with each successive

valid

CS falling edge. (See Shadow Regis-

ter, Table V, and Figure 3.) The channels

selected need not be consecutive.

If the SEQ and SHADOW Bits are set

in this way, then the sequence function

will not be interrupted upon completion

of the WRITE operation. This allows

other bits in the Control Register to be

altered while in a sequence without

terminating the cycle.

This configuration is used in conjunction

with the channel address bits ADD3 to

ADD0 to program continuous conver-

sions on a consecutive sequence of

channels from Channel 0 through to a

selected final channel as determined by

the channel address bits in the Control

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