AD7490 datasheet(4/24 Pages) AD

4 / 24 page

–4–

AD7490

REV. A

TIMING SPECIFICATIONS1

Limit at TMIN, TMAX

Parameter

VDD = 3 V

VDD = 5 V

Unit

Description

fSCLK

kHz min

MHz max

tCONVERT

tSCLK

tQUIET

ns min

Minimum Quiet Time Required between Bus

Relinquish and Start of Next Conversion

ns min

CS to SCLK Setup Time

ns max

Delay from

CS until DOUT Three-State Disabled

t3b

ns max

Delay from

CS to DOUT Valid

ns max

Data Access Time after SCLK Falling Edge

0.4 tSCLK

ns min

SCLK Low Pulsewidth

0.4 tSCLK

ns min

SCLK High Pulsewidth

ns min

SCLK to DOUT Valid Hold Time

15/50

ns min/max

SCLK Falling Edge to DOUT High Impedance

ns min

DIN Setup Time prior to SCLK Falling Edge

t10

ns min

DIN Hold Time after SCLK Falling Edge

t11

ns min

Sixteenth SCLK Falling Edge to

CS High

t12

µs max

Power-Up Time from Full Power-Down/

Auto Shutdown/Auto Standby Modes

NOTES

1Sample tested at 25

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

DD) and timed from a voltage level of 1.6 V.

(See Figure 1.) The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2Mark/Space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with V

DD = 3 V to give a throughput of 870 kSPS. Care must be

taken when interfacing to account for data access time t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK

frequency with which the user’s system can operate. (See Serial Interface section.)

3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 V

DRIVE V.

3b represents a worst-case figure for having ADD3 available on the DOUT line, i.e., if the AD7490 went back into three-state at the end of a conversion and some

other device took control of the bus between conversions, the user would have to wait a maximum time of t3b before having ADD3 valid on DOUT line. If the DOUT

line is weakly driven to ADD3 between conversions, then the user would typically have to wait 17 ns at 3 V and 12 ns at 5 V after the

CS falling edge before seeing

ADD3 valid on DOUT.

8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish

time of the part and is independent of the bus loading.

Specifications subject to change without notice.

(VDD = 2.7 V to 5.25 V, VDRIVE

≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)

AD7490 Datasheet(PDF) 4 Page - Analog Devices

AD7490 Datasheet(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL