HV582 datasheet(9/20 Pages) MICROCHIP

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DS20005455A-page 9

HV582

2.1

High-Voltage Output Pins

(HVOUT1 to HVOUT96)

These

are

the

high-voltage

output

channels

(Push-Pull).

2.2

High-Voltage Power Supply Pins

(VPP)

High-voltage power supply pins for the output channels

(HVOUTn).

2.3

High-Voltage Ground Pins (HVGND)

High-voltage ground pins provide the reference ground

level for the high-voltage output channels.

2.4

Logic Power Supply Pins (VDD)

Logic power supply pins for the 16-bit shift registers,

96-bit latch and decoders.

2.5

Data Input/Output Pins

(D1B, D2B, D3B, D4B, D5B, D6B)

Data Input/Output pins are configurable as inputs or

outputs for the shift registers depending on the state of

the Direction pin (DIR).

When DIR is High, pins D1B to D6B are configured as

inputs to the data shift registers. When DIR is Low,

these pins are configured as outputs of the data shift

registers.

2.6

Polarity Pin (POL)

The Polarity pin inverts the current state for all the

HVOUTn channels (from High to Low or Low to High)

when set High.

2.7

Output Enable Pin (OE)

The Output Enable pin controls the functionality of the

high-voltage output channels.

When OE is High, all HVOUTn channels are enabled and

form a push-pull configuration to operate according to

input data or OL, OH or POL configuration states. When

OE is Low, all HVOUTn channels are forced to a high-

impedance state, regardless of the data stored in the 96-

bit latch or the states of the OL, OH and POL pins.

2.8

Output Low Pin (OL)

The Output Low pin sets all high-voltage output chan-

nels (HVOUT1 to HVOUT96) to a Low level state

(HVGND).

When OL is set Low and OE is High, all the HVOUTn

channels are forced to a Low-level state (HVGND),

regardless of the data stored in the 96-bit latch. See

Table 1-2 for more information.

2.9

Output High Pin (OH)

The Output High pin sets all high-voltage output chan-

nels (HVOUT1 to HVOUT96) to a High-level state (VPP).

When OH is Low while OE and OL are High, all the

HVOUTn channels are forced to a High-level state

(VPP), regardless of the data stored in the 96-bit latch.

See Table 1-2 for more information.

2.10

Direction Pin (DIR)

The DIR pin controls the direction of the input data flow

for the input registers, whether it is clockwise (DnA to

DnB) or counter-clockwise (DnB to DnA).

When DIR is set High, data flows from DnB to DnA.

When DIR is set Low, data flows from DnA to DnB. See

Table 1-3 for more information.

2.11

Logic Ground Pins (GND)

Logic ground pins provide a reference ground level for

the low-voltage section of the IC, shift registers, latches

and decoders.

2.12

Reset Pin (RST)

The RST pin clears shift registers and the 96-bit latch

data content when it is set High. See Table 1-2 for

more information.

2.13

Latch Enable Pin (LE)

The Latch Enable pin controls the data transfer from the

input shift registers to the 96-bit latch and the HVOUTn

channels. See Table 1-2 for more information.

2.14

Clock Input Pin (CLK)

This is the clock input pin for the 16-bit input shift registers.

2.15

Data Input/Output Pins

(D1A, D2A, D3A, D4A, D5A, D6A)

The Data Input/Output pins are configurable as inputs

or outputs for the shift registers depending on the state

of the Direction pin (DIR).

When DIR is Low, pins D1A to D6A are configured as

inputs to the data shift registers. When DIR is High,

pins D1A to D6A are configured as outputs of the data

shift registers.

2.16

No Connection Pins (NC)

NC pins do not have any functionality on the IC. These

pins should not be connected.

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