INA148 datasheet(2/16 Pages) TI1

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INA148

SPECIFICATIONS: VS = ±5V to ±15V Dual Supplies

At TA = +25°C, RL = 10kΩ connected to ground and Ref pin connected to ground, unless otherwise noted.

INA148UA

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

OFFSET VOLTAGE (VO)

RTI(1)(2)

Input Offset Voltage

VOS

VS = ±15V, VCM = 0V

±1

±5mV

VS = ±5V, VCM = 0V

±1

±5mV

Drift

∆V

OS/∆T

At TA = –40°C to +85°C

±10

µV°C

vs Power Supply

PSRR

VS = ±1.35V to ±18V, VCM = 0V

±50

±400

µV/V

INPUT VOLTAGE RANGE

Common-Mode Voltage Range

VCM

VS = ±15V, (VIN

+ ) – (V

– ) = 0V

–200

+200

VS = ±5V, (VIN

+ ) – (V

– ) = 0V

–100

+80

Common-Mode Rejection

CMRR

VS = ±15V, VCM = –200V to +200V, RS = 0Ω

VS = ±5V, VCM = –100V to +80V, RS = 0Ω

INPUT IMPEDANCE

Differential

Ω

Common Mode

Ω

NOISE

RTI(1)(3)

Voltage Noise, f = 0.1Hz to 10Hz

µVp-p

Voltage Noise Density, f = 1kHz

880

nV/

√Hz

GAIN

Initial(1)

V/V

Gain Error

VO = (V–) + 0.5 to (V+) – 1.5

±0.01

±0.075

vs Temperature

±3

±10

ppm/

°C

Nonlinearity

VS = ±15V, VO = (V–) + 0.5 to (V+) – 1.5

±0.001

±0.002

% of FSR

VS = ±5V, VO = (V–) + 0.5 to (V+) – 1.5

±0.001

% of FSR

FREQUENCY RESPONSE

Small Signal Bandwidth

100

kHz

Slew Rate

1V/

µs

Settling Time: 0.1%

VS = ±15V, 10V Step

µs

0.01%

VS = ±15V, 10V Step

µs

0.1%

VS = ±5V, 6V Step

µs

0.01%

VS = ±5V, 6V Step

µs

Overload Recovery

50% Input Overload

µs

OUTPUT (VO)

Voltage Output

RL = 100kΩ

(V–) + 0.25

(V+) – 1

RL = 10kΩ

(V–) + 0.5

(V+) – 1.5

Output Current

Short-Circiuit Current

Continuous to Common

±13

Capacitive Load

Stable Operation

POWER SUPPLY

Operating Range, Dual Supplies

±1.35

±18

Quiescent Current

VIN = 0, IO = 0

±260

±300

µA

TEMPERATURE RANGE

Specified

–40

°C

Operating

–55

125

°C

Storage

–55

125

°C

Thermal Resistance

SO-8 Surface Mount

150

°C/W

NOTES: (1) Overall difference amplifier configuration. Referred to input pins (VIN

+ and V

– ), gain = 1V/V (2) Input offset voltage specification includes effects of

amplifier's input bias and offset currents. (3) Includes effects of input current noise and thermal noise contribution of resistor network.

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