OPA569 datasheet(19/28 Pages) TI1

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OPA569

SBOS264A

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5. Connect all holes, including those within the thermal pad

area and outside the pad area, to the internal ground

plane or other internal copper plane for single supply

applications, and V– for split-supply applications.

6. When laying out these holes to the ground plane, do not

use the typical web or spoke via connection methodology,

as shown in Figure 17. Web connections have a high

thermal resistance connection that is useful for slowing

the heat transfer during soldering operations. This makes

soldering the vias that have ground plane connections

easier. However, in this application, low thermal resis-

tance is desired for the most efficient heat transfer.

Therefore, the holes under the PowerPAD package should

make their connection to the internal ground plane with a

complete connection around the entire circumference of

the plated-through hole.

FIGURE 16. 20-Pin DWP PowerPAD PCB Etch and Via Pattern.

Web or Spoke Via

Solid Via

NOT RECOMMENDED

RECOMMENDED

FIGURE 17. Via Connection.

Thermal Land

299 mils x 510 mils

Minimum Area (7.59mm x 12.95mm)

(Copper)

OPTIONAL:

Additional 4 vias outside of

thermal pad area but under

the package

(Via diameter = 25 mils)

REQUIRED:

Thermal pad area: 140 mils x 176 mils

(3.56mm x 4.47mm) with 24 vias

(Via diameter = 13 mils)

9. With these preparatory steps in place, the PowerPAD IC

is simply placed in position and run through the solder

reflow operation as any standard surface-mount compo-

nent. This results in a part that is properly installed.

For detailed information on the PowerPAD package including

thermal modeling considerations and repair procedures,

please see Technical Brief SLMA002, “PowerPAD Thermally

Enhanced Package,” located at www.ti.com.

LAYOUT GUIDELINES

The OPA569 is a power amplifier that requires proper layout

for best performance. Figure 18 shows an example layout.

Refinements to this example layout may be required based

on assembly process requirements.

Keep power-supply leads as short as possible. This will keep

inductance low and resistive losses at a minimum. A mini-

mum of 18 gauge wire thickness is recommended for power-

supply leads. The wire length should be less than 8 inches.

Proper power-supply bypassing with low ESR capacitors is

essential to achieve good performance. A parallel combina-

tion of 100nF ceramic and 47

µF tantalum bypass capacitors

will provide low impedance over a wide frequency range.

Bypass capacitors should be placed as close as practical to

the power-supply pins of the OPA569.

PCB traces conducting high currents, such as from output to

load or from the power-supply connector to the power-supply

pins of the OPA569 should be kept as wide and short as

possible.

The twenty-four holes in the landing pattern for the OPA569

are for the thermal vias that connect the PowerPAD of the

OPA569 to the heatsink area on the PCB. The additional four

larger vias further enhance the heat conduction into the

heatsink area. All traces conducting high currents are very

wide for lowest inductance and minimal resistive losses. Note

that the negative supply (–V) pin on the OPA569 can be

connected through the PowerPAD to allow for maximum

trace width for high current paths.

7. The top-side solder mask should leave the terminals of the

pad connections and the thermal pad area exposed. The

thermal pad area should leave the 13 mil holes exposed.

The larger holes outside the thermal pad area should be

covered with solder mask.

8. Apply solder paste to the exposed thermal pad area and

all of the package terminals.

FIGURE 18. 20-Pin DWP PowerPAD PCB Etch and Via

Pattern.

V–

Parellel

Out 1

Current

Limit Set

Current Limit Flag

–In

+In

Thermal Flag

Enable

MONITOR

V–

OUT

V+

Parallel Out 2

Pin 1

NOTE: Avoid routing Current

Limit Set and Current Limit

Flag traces closely in parallel.

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