OPA643P datasheet(8/18 Pages) TI1

8 / 18 page

OPA643

Gain,

= 1 +

Ω

–V

–5V

+5V

Ω Load

OPA643

Ω

100

Ω

402

Ω

Ω Source

0.1µF

2.2µF

0.1µF

APPLICATIONS INFORMATION

TYPICAL APPLICATION AND

CHARACTERIZATION CIRCUIT

The OPA643’s combination of speed and dynamic range is

easily achieved in a wide variety of application circuits,

providing that simple guidelines common to all high speed

amplifiers are observed. For example, good power supply

decoupling, as shown in Figure 1, is essential to achieve the

lowest possible harmonic distortion and smooth frequency

response. Careful PC board layout and component selection

will maximize the performance of the OPA643 in all

applications, as discussed in the remaining sections of this

data sheet.

Figure 1 shows the gain of +5 configuration used as the basis

for most of the Typical Performance Curves. Most of the

curves were characterized using signal sources with 50

Ω

driving impedance, and with measurement equipment

presenting 50

Ω load impedance. In Figure 1, the 50Ω shunt

resistor at the VI terminal matches the source impedance of

the test generator, while the 50

Ω series resistor at the V

terminal provides a matching resistor for the measurement

equipment load. Generally, data sheet specifications refer to

the voltage swing at the output pin (VO in Figure 1). The

total 100

Ω load from the series and shunt matching resistors,

combined with the 502

Ω total feedback network load, presents

the OPA643 with an effective output load of approximately

Ω.

BUFFERING HIGH PERFORMANCE ADC’S

To achieve full performance from a high dynamic range

A/D converter, considerable care must be exercised in the

design of the input amplifier interface circuit. The example

circuit on the front page shows a typical AC-coupled interface

to a very high dynamic range converter. This circuit uses a

new external compensation technique which stabilizes the

OPA643 for low signal gain, while maintaining the high

gain bandwidth, fast slew rate and improved distortion

performance of the decompensated architecture. Testing

shows that a high loop gain and flat response are maintained

through the Nyquist frequency on this circuit using the

ADS805 giving very high SFDR

performance. Above

Nyquist, the loop gain is rolled off sharply to lower the

crossover frequency, and finally additional lead is introduced

at crossover to maintain good phase margin. In general, this

loop gain shaping technique allows the use of high gain

bandwidth, decompensated op amps to achieve better dynamic

performance in low signal gain applications. Refer to the

section on Low Gain Operation for further information.

The frequency domain digitizer application on the front page

allows the signal swing at the output of the OPA643 to be

operated at an optimum DC point. Centering the output

swing between the supplies is a good starting point, but

significant improvement in second-harmonic distortion can

be achieved by shifting the output DC point away from

ground. A typical signal swing of 2Vp-p, operating at either

an optimized or a ground-centered output DC voltage, is

then level shifted through the blocking capacitor to a DC

reference level at the converter input. This reference voltage

is created by a well decoupled resistive divider off the

converter’s internal reference voltages. To have negligible

effect on the rated spurious-free dynamic range (SFDR) of

the converter, the amplifier’s SFDR should be at least 10dB

greater. In the front page example, the insertion of the

OPA643 has an unmeasurable effect on the distortion of the

20MSPS ADS805, which achieves 80dB SFDR at a 10MHz

Nyquist input signal.

To deliver the lowest possible distortion using the 8-pin

SO-8 or DIP package, additional 0.1

µF power supply

decoupling capacitors on pins 5 and 8 are required. These

are shown in Figure 1. Although pins 5 and 8 are internally

connected to pins 4 and 7 respectively (the standard supply

pins for 8-pin op amps), the additional capacitors help to

decouple the package lead inductances and decrease the

second-harmonic distortion for a 5MHz fundamental by

approximately 4dB. The much shorter bond wires and supply

leads of the SOT23-5 package give the best distortion

performance while requiring only two power supply

connections.

Successful application to ADC buffering requires a careful

selection of the series resistor at the output of the OPA643,

along with the additional shunt capacitor at the ADC input.

To some extent, selection of this RC network will be

determined empirically for each model of converter. Many

high performance CMOS ADC’s, like the ADS805, perform

better with an additional capacitor to ground on the input

FIGURE 1. Gain of +5, High Frequency Application and

Characterization Circuit (P or U Package).

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