OPA685 datasheet(21/32 Pages) TI1

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OPA685

For a 20mA peak output current DAC, the mid-scale current

of 10mA will give a 2V DC output common-mode operating

voltage due to the 200

Ω resistor to ground at their outputs. The

total AC impedance at each output is 50

Ω, giving a ±0.5V

swing around this 2V common-mode voltage for the DAC.

These resistors also act as a current divider sending 75% of the

DAC output current through the feedback resistor (464

Ω). The

blocking capacitor references the OPA685 output voltage to

ground, and turns the unipolar DAC output current into a

bipolar swing of 0.75 • 20mA • 464

Ω = 7Vp-p at each

amplifier output. Each output is exactly 180

° out-of-phase

from the other, producing double 7Vp-p into the matching

resistors. To limit the peak output current and improve distor-

tion, the circuit of Figure 10 is set up with a 1.4:1 step-down

transformer. This reflects the 50

Ω load to be 100Ω at the

primary side of the transformer. For the maximum 14Vp-p

swing across the outputs of the two amplifiers, the matching

resistors will drop this to 7Vp-p at the input of the transformer,

then down to 5Vp-p maximum at the 50

Ω load at the output

of the transformer.

HIGH-SPEEDADC INPUT DRIVERS

The OPA685 is ideally suited to the demanding input drive

requirements of emerging ultra high-speed and high perfor-

mance ADCs. As a single amplifier stage, 10-bit converters

through 100MSPS may be driven, while 8-bit converters

may be driven with input frequencies in excess of 100MHz.

Emerging differential input ADCs can also benefit from a

purely differential input interface using two OPA685s to get

a significant improvement in even-order harmonics along

with a somewhat improved 3rd-order harmonic suppression.

SINGLE-ENDED ADC INPUT INTERFACE

Figure 11 shows an example single +5V supply ADC driver

where the AC gain is set to –8V/V. The converter is shown

with both an inverting and non-inverting input. The inverting

input is used here to make the overall channel non-inverting.

The Typical Performance Curves for the non-inverting gain

of +8 show very flat frequency response for +5V only

operation when driving into the 20pF load capacitor shown in

Figure 11. The inverting configuration of Figure 11 was

selected for higher slew rate and lower distortion perfor-

mance. It will give > 300MHz bandwidth at this gain of –8.

Harmonic distortion for a 2Vp-p output signal will be < –

50dBc through 50MHz.

DIFFERENTIAL ADC DRIVER

For applications requiring the lowest harmonic distortion

through very high frequencies, a balanced differential cir-

cuit using the OPA685 offers the best performance. Figure

12 shows an example of this approach where an input step-

up transformer is used to convert to a differential signal and

improve the Noise Figure.

FIGURE 11. Single Supply, Wideband ADC Driver.

FIGURE 12. Very Wideband Differential ADC Driver.

OPA685

42.2

Ω

O = 2.5VDC – 8VI

400

Ω

+5V

Power supply decoupling

not shown.

+5V

ADC

Ω

0.1

µF

20pF

DIS

+5V

–5V

OPA685

22pF

+5V

–5V

600

Ω

OPA685

1:2

Ω Source

Noise

Figure

11.8dB

600

Ω

100

Ω

100

Ω

43.2

Ω

Power supply decoupling

not shown.

43.2

Ω

ADC Input

= 12V/V (21.6dB)

DIS

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