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TPS51116MPWPREP Datasheet(PDF) 15 Page - Texas Instruments

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Part # TPS51116MPWPREP
Description  COMPLETE DDR, DDR2, DDR3, AND LPDDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 1-A LDO, BUFFERED REFERENCE
PDF  38 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS51116MPWPREP Datasheet(HTML) 15 Page - Texas Instruments

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background image
I
OCP +
V
TRIP
R
DS(on)
)
I
RIPPLE
2
+
V
TRIP
R
DS(on)
)
1
2
L
f
V
IN * VOUT
V
OUT
V
IN
V
TRIP (mV) + RTRIP (kW)
10 (mA)
TPS51116-EP
www.ti.com
SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
VDDQ and VTT Discharge Control
TPS51116 discharges VDDQ, VTTREF and VTT outputs when S3 and S5 are both low. There are two different
discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3.
Table 3. Discharge Selection
MODE
DISCHARGE MODE
V5IN
No discharge
VDDQ
Tracking discharge
GND
Non-tracking discharge
When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors
and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via
VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can
handle up to 1 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off
and the operation mode is changed to the non-tracking-discharge mode.
When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are
connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.
Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In no discharge mode,
TPS51116 does not discharge any output charge.
Current Protection for VDDQ
The SMPS has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. The
trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme
section). For resistor sensing scheme, the trip level, VTRIP, is fixed value of 60 mV.
For RDS(on) sensing scheme, CS terminal sinks 10 μA and the trip level is set to the voltage across this RTRIP
resistor.
(4)
As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load
current at overcurrent threshold, IOCP, can be calculated as shown in Equation 5.
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. If the output voltage becomes less than Powergood level, the VTRIP is cut into half and
the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and
shutdown.
Current Protection for VTT
The LDO has an internally fixed constant overcurrent limiting of 3.8 A while operating at normal condition. This
trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of
±10% of the target voltage.
Copyright © 2012, Texas Instruments Incorporated
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