TPS51116-EP

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SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012

Layout Considerations

Certain points must be considered before designing a layout using the TPS51116.

•

PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET

and high-voltage side of the inductor, should be as short and wide as possible.

•

Consider adding a small snubber circuit, consisting of a 3-

Ω resitor and a 1-nF capacitor, between LL and

PGND in case a high-frequency surge is observed on the LL voltage waveform.

•

All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage

switching nodes such as LL, DRVL or DRVH nodes to avoid coupling.

•

VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for

VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide

connection.

•

The output capacitor for VTT should be placed close to the pin with short and wide connection in order to

avoid additional ESR and/or ESL of the trace.

•

VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the

high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to

sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.

Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and

the output capacitor(s).

•

Consider adding LPF at VTTSNS when the ESR of the VTT output capacitor(s) is larger than 2 m

Ω.

•

VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference

voltage of VTTREF. Avoid any noise generative lines.

•

Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding

common impedance to the high current path of the VTT source/sink current.

•

GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND

to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid

additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.

•

PGND is the return path for rectifying MOSFET gate drive. Use 0.65 mm (25mil) or wider trace. Connect to

source of rectifying MOSFET with shortest possible path.

•

The trace from the CS pin should avoid high-voltage switching nodes such as those for LL, VBST, DRVH,

DRVL or PGOOD.

•

In order to effectively remove heat from the package, prepare thermal land and solder to the package’s

thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.

Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground

plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the

package.

Figure 6. D-CAP™ Mode

Copyright © 2012, Texas Instruments Incorporated

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Product Folder Links: TPS51116-EP