TPS51116MPWPREP datasheet(19/38 Pages) TI1

19 / 38 page

0 +

ESR

R1 +

OUT * 0.75

0.75

z1 +

TPS51116-EP

www.ti.com

SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012

6. Calculate CC. The purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it

causes phase delay, another zero to cancel this effect at f0 frequency is need. This zero, ωz1, is determined

by Cc and Rc. Recommended

ωz1 is 10 times lower to the f0 frequency.

(22)

7. When using adjustable mode, determine the value of R1 and R2. .

(23)

D-CAP™ Mode Operation

A buck converter system using D-CAP™ Mode can be simplified as below.

Figure 5. Linearizing the Modulator

The PWM comparator compares the VDDQSNS voltage divided by R1 and R2 with internal reference voltage,

and determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is high

enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The

DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage

increase.

For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.

(24)

As f0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP™ mode is determined

by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have CO in the order of

several 100

μF and ESR in range of 10 mΩ. These makes f0 in the order of 100 kHz or less and the loop is then

stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational

mode.

Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external components

configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient

amount of feedback signal needs to be provided by external circuit to reduce jitter level.

The required signal level is approximately 15 mV at comparing point. This gives VRIPPLE = (VOUT/0.75) x 15 (mV)

at the output node. The output capacitor’s ESR should meet this requirement.

The external components selection is much simple in D-CAP™ mode.

1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the

Current Mode Operation section.

2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are

recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in

Submit Documentation Feedback

Product Folder Links: TPS51116-EP

TPS51116MPWPREP Datasheet(PDF) 19 Page - Texas Instruments

TPS51116MPWPREP Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL