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TPS51513 Datasheet(PDF) 13 Page - Texas Instruments |
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TPS51513 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 39 page ![]() ( ) CS CSINT OUT DROOP DROOP M droop R A I V R G ´ ´ = ´ DROOP L L OUT V R I - = - UDG-09079 + 11 V – 12 V L – 1 V + 1 V C Q1 on Q2 on Q1 Q2 L V I t L D = D TPS51513 www.ti.com SLUS956A – JUNE 2009 – REVISED FEBRUARY 2010 Droop or No-Droop Compensation The TPS51513 can be designed to either provide a linear load line (also known as droop) or operate with a flat load-line (no-droop). This is achieved by the component topology at the DROOP pin. Droop is obtained by putting a resistor from DROOP to VREF (RDROOP) to limit the gain of the error amplifier. The equation for droop is shown in Equation 2. where • RCS is the effective current sense resistance, whether a sense resistor or inductor DCR is used • ACSINT is the gain of the current sense amplifier • IOUT is the output current, • GMDROOP is the GM of the droop amplifier. (2) The load-line is defined by the change in output voltage vs. the change in current. (3) The TPS51513 also has the ability to provide an output without a load line. In this case, referring to Figure 2, R2 is left open, and R1 and C2 are populated to break the DC path between DROOP and REF and providing very high DC loop gain. Means to select R1 and C2 are given in the Design Procedure section. Overshoot Reduction (OSR™) Feature The problem of overshoot in low duty-cycle synchronous buck converters is well known, and results from the output inductor having a small voltage (VCORE) with which to respond to a transient load release. In Figure 5, with ideal components and the common values of 12-V input and 1-V output, the inductor voltage (VL) with the upper FET on is 11 V (12V – 1V). With the lower FET on, the inductor voltage is only 1 V. Figure 5. Representative Schematic of a Synchronous Converter Because , the converter can respond much more quickly to a load step than it can to a load release. The idea of OSR is to turn off the lower FET during a transient load release to force the inductor current through the body diode of the lower FET, thus increasing the voltage across the inductor to VCORE + VDIODE. This discharges the inductor more quickly and reduces the peak voltage of the transient overshoot. As a result, less output capacitance is required to achieve a given output tolerance specification. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s) :TPS51513 |
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