LM4852 datasheet(13/21 Pages) NSC

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Application Information

2C PIN DESCRIPTION

SDA: This is the serial data input pin.

SCL: This is the clock input pin.

ADR: This is the address select input pin.

2C INTERFACE

The LM4852 uses a serial bus, which conforms to the I

protocol, to control the chip’s functions with two wires: clock

and data. The clock line is uni-directional. The data line is

bi-directional (open-collector) with a pullup resistor (typically

10k

Ω).The maximum clock frequency specified by the I2C

standard is 400kHz. In this discussion, the master is the

controlling microcontroller and the slave is the LM4852.

The I

2C address for the LM4852 is determined using the

ADR pin. The LM4852’s two possible I

2C chip addresses are

of the form 110110X

10 (binary), where the X1 = 0, if ADR is

logic low; and X

1 = 1, if ADR is logic high. If the I

2C interface

is used to address a number of chips in a system and the

LM4852’s chip address can be changed to avoid address

conflicts.

The timing diagram for the I

2C is shown in Figure 2. The data

is latched in on the stable high level of the clock and the data

line should be held high when not in use. The timing diagram

is broken up into six major sections:

The “start” signal is generated by lowering the data signal

while the clock signal is high. The start signal will alert all

devices attached to the I

2C bus to check the incoming ad-

dress against their own chip address.

The 8-bit chip address is sent next, most significant bit first.

Each address bit must be stable while the clock level is high.

After the last bit of the address is sent, the master checks for

the LM4852’s acknowledge. The master releases the data

line high (through a pullup resistor). Then the master sends

a clock pulse. If the LM4852 has received the address

correctly, then it holds the data line low during the clock

pulse. If the data line is not low, then the master should send

a “stop” signal (discussed later) and abort the transfer.

The 8 bits of data are sent next, most significant bit first.

Each data bit should be valid while the clock level is stable

high.

After the data byte is sent, the master must generate another

acknowledge to see if the LM4852 received the data.

If the master has more data bytes to send to the LM4852,

then the master can repeat the previous two steps until all

data bytes have been sent.

The “stop” signal ends the transfer. To signal “stop”, the data

signal goes high while the clock signal is high.

200606F5

FIGURE 2. I

2C Bus Format

200606F4

FIGURE 3. I

2C Timing Diagram

LM4852 Datasheet(PDF) 13 Page - National Semiconductor (TI)

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