AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified (Note 4)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T

SET

Input to SEL Setup Time, Figures 1, 2

(Note 5)

0.7

0.5

ns

T

HOLD

Input to SEL Hold Time, Figures 1, 2

(Note 5)

1.0

0.5

ns

T

SWITCH

SEL to Switched Output, Figures 1, 2

0.9

1.2

1.7

ns

T

PHZ

Disable Time (Active to TRI-STATE) High to Z, Figure 3

2.1

4.0

ns

T

PLZ

Disable Time (Active to TRI-STATE) Low to Z, Figure 3

3.0

4.5

ns

T

PZH

Enable Time (TRI-STATE to Active) Z to High, Figure 3

25.5

55.0

ns

T

PZL

Enable Time (TRI-STATE to Active) Z to Low, Figure 3

25.5

55.0

ns

T

LHT

Output Low-to-High Transition Time, 20% to 80%, Figure 5

290

400

580

ps

T

HLT

Output High-to-Low Transition Time, 80% to 20%, Figure 5

290

400

580

ps

T

JIT

LVDS Data Path Peak to Peak Jitter,

(Note 6)

V

V

40

90

ps

V

pattern; V

75

190

ps

T

PLHD

Propagation Low to High Delay, Figure 6

0.9

1.3

1.6

ns

Propagation Low to High Delay, Figure 6

V

1.0

1.3

1.5

ns

T

PHLD

Propagation High to Low Delay, Figure 6

0.9

1.3

1.6

ns

Propagation High to Low Delay, Figure 6

V

1.0

1.3

1.5

ns

T

SKEW

Pulse Skew |T

0

225

ps

T

CCS

Output Channel-to-Channel Skew, Figure 7

35

80

ps

Note 4: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and

temperature) range.

Note 6: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT range with the following

equipment test setup: HP70004A (display mainframe) with HP70841B (pattern generator), 5 feet of RG-142 cable with DUT test board and HP83480A (digital scope

mainframe) with HP83483A (20GHz scope module).

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