DS90CP22 Pin Description

Pin Name

# of Pin

Input/Output

Description

IN+

2

I

Non-inverting LVDS input

IN -

2

I

Inverting LVDS input

OUT+

2

O

Non-inverting LVDS Output

OUT -

2

O

Inverting LVDS Output

EN

2

I

A logic low on the Enable puts the LVDS output into

TRI-STATE and reduces the supply current

SEL

2

I

2:1 mux input select

GND

1

P

Ground

V

CC

1

P

Power Supply

NC

2

No Connect

Application Information

MODES OF OPERATION

The DS90CP22 provides three modes of operation. In the

1:2 splitter mode, the two outputs are copies of the same

single input. This is useful for distribution / fan-out applica-

tions. In the repeater mode, the device operates as a 2

channel LVDS buffer. Repeating the signal restores the

LVDS amplitude, allowing it to drive another media segment.

This allows for isolation of segments or long distance appli-

cations. The switch mode provides a crosspoint function.

This can be used in a system when primary and redundant

paths are supported in fault tolerant applications.

INPUT FAIL-SAFE

The receiver inputs of the DS90CP22 do not have internal

fail-safe biasing. For point-to-point and multidrop applica-

tions with a single source, fail-safe biasing may not be

required. When the driver is off, the link is in-active. If fail-

safe biasing is required, this can be accomplished with ex-

ternal high value resistors. The IN+ should be pull to Vcc with

10k

Ω and the IN− should be pull to Gnd with 10kΩ. This

provides a slight positive differential bias, and sets a known

HIGH state on the link with a minimum amount of distortion.

UNUSED LVDS INPUTS

Unused LVDS Receiver inputs should be tied off to prevent

the high-speed sensitive input stage from picking up noise

signals. The open input to IN+ should be pull to Vcc with

10k

Ω and the open input to IN− should be pull to Gnd with

10k

Ω.

UNUSED CONTROL INPUTS

The SEL and EN control input pins have internal pull down

devices. Unused pins may be tied off or left as no-connect (if

a LOW state is desired).

EXPANDING THE NUMBER OF OUTPUT PORTS

To expand the number of output ports, more than one

DS90CP22 can be used. Total propagation delay through the

devices should be considered to determine the maximum

expansion. For example, if2X4is desired, than three of the

DS90CP22 are required. A minimum of two device propaga-

tion delays (2 x 1.3ns = 2.6ns (typ)) can be achieved. For a

2 X 8, a total of 7 devices must be used with propagation

delay of 3 x 1.3ns = 3.9ns (typ). The power consumption will

increase proportional to the number of devices used.

PCB LAYOUT AND POWER SYSTEM BYPASS

Circuit board layout and stack-up for the DS90CP22 should

be designed to provide noise-free power to the device. Good

layout practice also will separate high frequency or high level

inputs and outputs to minimize unwanted stray noise pickup,

feedback and interference. Power system performance may

be greatly improved by using thin dielectrics (4 to 10 mils) for

power/ground sandwiches. This increases the intrinsic ca-

pacitance of the PCB power system which improves power

supply filtering, especially at high frequencies, and makes

the value and placement of external bypass capacitors less

critical. External bypass capacitors should include both RF

ceramic and tantalum electrolytic types. RF capacitors may

use values in the range 0.01 µF to 0.1 µF. It is recommended

practice to use two vias at each power pin of the DS90CP22

as well as all RF bypass capacitor terminals. Dual vias

reduce the interconnect inductance by up to half, thereby

reducing interconnect inductance and extending the effec-

tive frequency range of the bypass components.

The outer layers of the PCB may be flooded with additional

ground plane. These planes will improve shielding and iso-

lation as well as increase the intrinsic capacitance of the

power supply plane system. Naturally, to be effective, these

planes must be tied to the ground supply plane at frequent

intervals with vias. Frequent via placement also improves

signal integrity on signal transmission lines by providing

short paths for image currents which reduces signal distor-

tion.

There are more common practices which should be followed

when designing PCBs for LVDS signaling. Please see Appli-

cation Note: AN-1108 for additional information.

COMPATIBILITY WITH LVDS STANDARD

The DS90CP22 is compatible with LVDS and Bus LVDS

Interface devices. It is enhanced over standard LVDS drivers

in that it is able to driver lower impedance loads with stan-

dard LVDS levels. Standard LVDS drivers provide 330mV

differential output with a 100

Ω load. The DS90CP22 pro-

vides 365mV with a 75

Ω load or 400mV with 100Ω loads.

This extra drive capability is useful in certain multidrop ap-

plications.

In backplane multidrop configurations, with closely spaced

loads, the effective differential impedance of the line is re-

duced. If the mainline has been designed for 100

Ω differen-

tial impedance, the loading effects may reduce this to the

70

Ω range depending upon spacing and capacitance load.

Terminating the line with a 75

Ω load is a better match than

with 100

Ω and reflections are reduced.

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