SI5347 datasheet(2/55 Pages) SILABS

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1. Feature List

The Si5347/46-D features are listed below:

• Four or two DSPLLs to synchronize to multiple inputs

• Generates any combination of output frequencies from any in-

put frequency

• Ultra low jitter:

• 95 fs typ (12 kHz – 20 MHz)

• Input frequency range:

• Differential: 8 kHz to 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range:

• Differential: up to 712.5 MHz

• LVCMOS: up to 250 MHz

• Flexible crosspoints route any input to any output clock

• Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz

to 4 kHz

• Highly configurable outputs compatible with LVDS, LVPECL,

LVCMOS, CML, and HCSL with programmable signal ampli-

tude

• Status monitoring (LOS, OOF, LOL)

• Hitless input clock switching: automatic or manual

• Locks to gapped clock inputs

• Automatic free-run and holdover modes

• Fastlock feature for low nominal bandwidths

• Glitchless on-the-fly DSPLL frequency changes

• DCO mode: as low as 0.01 ppb steps per DSPLL

• Core voltage:

• VDD: 1.8 V ±5%

• VDDA: 3.3 V ±5%

• Independent output clock supply pins: 3.3, 2.5, or 1.8 V

• Output-output skew:

• Using same DSPLL: 65 ps (Max)

• Serial interface: I2C or SPI

• In-circuit programmable with non-volatile OTP memory

• ClockBuilder™ Pro software tool simplifies device configuration

• Si5347: Quad DSPLL, 4 input, 8 output, 64-QFN 9×9 mm

• Si5346: Dual DSPLL, 4 input, 4 output, 44-QFN 7×7 mm

• Temperature range: –40 to +85 °C

• Pb-free, RoHS-6 compliant

Si5347/46 Rev D Data Sheet

Feature List

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