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HT95A400 Datasheet(PDF) 17 Page - Holtek Semiconductor Inc |
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HT95A400 Datasheet(HTML) 17 Page - Holtek Semiconductor Inc |
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17 / 48 page  HT95AXXX Rev. 1.20 17 May 26, 2004 Register Addr. Reset Conditions Power On RES Pin RES Pin (Sleep/Idle) WDT WDT (Sleep/Idle) DTMFC 20H ---- -0-1 ---- -0-1 ---- -0-1 ---- -0-1 ---- -u-u DTMFD 21H 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu LINE 22H 0--- ---- u--- ---- u--- ---- u--- ---- u--- ---- RTCC 24H 0-0- ---- u-u- ---- u-u- ---- u-u- ---- u-u- ---- MODE 26H 000- ---- 00u- ---- 00u- ---- 00u- ---- 000- ---- PFDC 2EH 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu ---- PFDD 2FH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PF 34H 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PFC 35H 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PG 36H ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu PGC 37H ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu RAM (Data & LCD) x u u u u Note: ²u² means ²unchanged² ²x² means ²unknown² ²-² means ²unused² Timer/Event Counter Two timer/event counters (TMR0, TMR1) are imple- mented in the telephone controller series. The Timer/Event Counter 0 and Timer/Event Counter 1 con- tain 16-bits programmable count-up counter and the clock may come from an external or internal source. For TMR0, the internal source is the instruction clock (sys- tem clock/4). For TMR1, the internal source is 32768Hz. Using the 32768Hz clock or instruction clock, there is only one reference time-base. The external clock input allows the user to count external events, measure time intervals or pulse width, or generate an accurate time base. There are 3 registers related to the Timer/Event Counter 0; TMR0H, TMR0L and TMR0C. Writing TMR0L only writes the data into a low byte buffer, but writing TMR0H simultaneously writes the data along with the contents of the low byte buffer into the Timer/Event Counter 0 preload register (16-bit). The Timer/Event Counter 0 preload register is changed by writing TMR0H opera- tions. Writing TMR0L will keep the Timer/Event Counter 0 preload register unchanged. Reading TMR0H latches the TMR0L into the low byte buffer to avoid a false timing problem. Reading TMR0L returns the contents of the low byte buffer. In other words, the low byte of the Timer/Event Counter 0 can not be read directly. It must read the TMR0H first to make the low byte contents of Timer/Event Counter 0 be latched into the buffer. There are 3 registers related to the Timer/Event Counter 1; TMR1H, TMR1L and TMR1C. The Timer/Event Counter 1 operates in the same manner as the Timer/Event Counter 0. The TMR0C is the Timer/Event Counter 0 control regis- ter, which defines the Timer/Event Counter 0 options. The Timer/Event Counter 1 has the same options as the Timer/Event Counter 0 and is defined by TMR1C. The timer/event counter control registers define the operat- ing mode, counting enable or disable and active edge. T 0 M 1 / T 1 M 1 T 0 M 0 / T 1 M 0 T M R 1 T M R 0 T 0 E / T 1 E T 0 M 1 / T 1 M 1 T 0 M 0 / T 1 M 0 T 0 O N / T 1 O N P u l s e W i d t h M e a s u r e m e n t M o d e C o n t r o l T i m e r / E v e n t C o u n t e r 0 / 1 P r e l o a d R e g i s t e r T i m e r / e v e n t C o u n t e r 0 / 1 D a t a B u s R e l o a d O v e r f l o w t o I n t e r r u p t T i m e r 0 : I n s t r u c t i o n c l o c k ( s y s t e m c l o c k / 4 ) T i m e r 1 : 3 2 7 6 8 H z L o w B y t e B u f f e r * N o t e : * T M R 1 p i n i s n o t s u p p o r t e d f o r H T 9 5 A 1 0 0 / 1 0 P . Timer/Event Counter 0/1 |
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