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HT95A400 Datasheet(PDF) 19 Page - Holtek Semiconductor Inc |
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HT95A400 Datasheet(HTML) 19 Page - Holtek Semiconductor Inc |
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19 / 48 page  HT95AXXX Rev. 1.20 19 May 26, 2004 Each I/O line has its own control register (PAC, PBC, PDC, PEC, PFC, PGC) to control the input/output con- figuration. With this control register, CMOS output or Schmitt trigger input can be reconfigured dynamically under software control. To make one I/O line to function as an input line, the corresponding latch of the control register must be written with a ²1². The pull-high resis- tance shows itself automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. For output function, CMOS is the only configuration. Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H, 18H, 1AH, 34H or 36H) instructions. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i ², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. They are selected by mask option per bit. There is a pull-high option available for all I/O lines. Once the pull-high option of an I/O line is selected, the I/O lines have pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode may cause a floating state. I/O port pull-high, wake-up function are selected by mask option I/O Port Output Input Supported for HT95AXXX Pull-high Resistor Wake-up Function 400/P 300/P 200/P 100/P PA7~PA0 CMOS Selected per bit Selected per bit ÖÖÖÖ PB7~PB0 CMOS Selected per bit ¾ ÖÖÖÖ PD3~PD0 CMOS Selected per nibble ¾ ÖÖÖÖ PD7~PD4 CMOS Selected per nibble ¾ ÖÖÖ ¾ PE3~PE0 CMOS Selected per nibble ¾ ÖÖÖ ¾ PE7~PE4 CMOS Selected per nibble ¾ Ö ¾¾¾ PF7~PF0 CMOS Selected per nibble ¾ Ö ¾¾¾ PG3~PG0 CMOS Selected per nibble ¾ Ö ¾¾¾ Note: ²¾² means unavailable V D D A l l I / O P i n s M U X P A W a k e - u p O p t i o n 0 ~ 7 S y s t e m W a k e - u p ( P A o n l y ) R e a d D a t a R e g i s t e r D Q C K Q B S D Q C K Q B S C o n t r o l B i t P U D a t a B u s W r i t e C o n t r o l R e g i s t e r C h i p R e s e t R e a d C o n t r o l R e g i s t e r W r i t e D a t a R e g i s t e r D a t a B i t Input/Output Ports |
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