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HT95A400 Datasheet(PDF) 18 Page - Holtek Semiconductor Inc |
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HT95A400 Datasheet(HTML) 18 Page - Holtek Semiconductor Inc |
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18 / 48 page  HT95AXXX Rev. 1.20 18 May 26, 2004 The T0M0/T1M0, T0M1/T1M1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0 or TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the instruction clock (TMR0) or 32768Hz (TMR1). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0 or TMR1). The counting is based on the 32768Hz clock for TMR1 or instruction clock for TMR0. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. If an over- flow occurs, the counter is reloaded from the timer/event counter preload register and generates the correspond- ing interrupt request flag (T0F/T1F) at the same time. Note that the event count mode is not available for Timer1 of HT95A100/10P. In pulse width measurement mode with the T0ON/ T1ON and T0E/T1E bits equal to 1, once the TMR0/TMR1 pin has received a transient from low to high (or high to low; if the T0E/T1E bit is 0) it will start counting until the TMR0/TMR1 pin returns to the original level and resets the T0ON/T1ON. The measured result will remain in the timer/event counter even if the acti- vated transient occurs again. In other words, only 1 cy- cle measurement can be done. Until setting the T0ON/T1ON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and continue to measure the width and issues the interrupt request just like the other two modes. Note that this mode is not available for Timer1 of HT95A100/10P. To enable the counting operation, the timer on bit (T0ON/T1ON) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON will be cleared automatically after the measurement cycle is com- pleted. But in the other two modes the T0ON/T1ON can only be reset by instruction. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writinga0to ET0I/ET1I can disable the corresponding interrupt ser- vice. In the case of timer/event counter off condition, writing data to the timer/event counter preload register also re- loads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is reserved only in the timer/event counter preload register. The timer/event counter will go on operating until an overflow occurs. Input/Output Ports There is a maximum of 44 bidirectional input/output lines in the HT95AXXX family MCU, labeled as PA, PB, PD, PE, PF and PG. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H, 18H, 1AH, 34H or 36H). For output oper- ation, all the data is latched and remains unchanged un- til the output latch is rewritten. Regis- ter Label Bits R/W Function TMR0C (0EH) / TMR1C (11H) ¾ 0~2 RO Unused bit, read as ²0² T0E/T1E 3 RW To define the TMR0/TMR1 active edge of timer For event count or Timer mode (0=active on low to high; 1=active on high to low) For pulse width measurement mode (0=measures low pulse width; 1=measures high pulse width) T0ON/T1ON 4 RW To enable/disable timer counting (0=disabled; 1=enabled) ¾ 5RO Unused bit, read as ²0² T0M0/T1M0 T0M1/T1M1 6 7 RW To define the operating mode Bit 7, 6=01, Event count mode (external clock) Bit 7, 6=10, Timer mode Bit 7, 6=11, Pulse width measurement mode Bit 7, 6=00, Unused Register Bits R/W Function TMR0H (0CH) 0~7 RW Timer/Event Counter 0 higher-order byte register TMR0L (0DH) 0~7 RW Timer/Event Counter 0 lower-order byte register TMR1H (0FH) 0~7 RW Timer/Event Counter 1 higher-order byte register TMR1L (10H) 0~7 RW Timer/Event Counter 1 lower-order byte register |
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