GS8342D06 datasheet(14/30 Pages) GSI

14 / 30 page

20% tKHKH

VSS – 1.0 V

50%

VSS

VIH

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKHKH

VDD + 1.0 V

50%

VDD

VIL

Note:

Input Undershoot/Overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

oC, f = 1 MHZ, VDD = 1.8 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance

CIN

VIN = 0 V

Output Capacitance

COUT

VOUT = 0 V

Clock Capacitance

CCLK

VIN = 0 V

Note:

This parameter is sample tested.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02a 11/2012

14/30

GS8342D06/11/20/38BD-550/500/450/400/350

AC Test Conditions

Parameter

Conditions

Input high level

1.25 V

Input low level

0.25 V

Max. input slew rate

2 V/ns

Input reference level

0.75 V

Output reference level

VDDQ/2

Note:

Test conditions as specified with output loading as shown unless otherwise noted.

VT = 0.75 V

RQ = 250

Ω (HSTL I/O)

VREF = 0.75 V

AC Test Load Diagram

(TA = 25

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