GS8342T08/09/18/36BD-400/350/333/300/250

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02 6/2012

19/35

© 2011, GSI Technology

Hold Times

Address Input Hold Time

0.4

—

0.4

—

0.4

—

0.4

—

0.5

—

ns

1

Control Input Hold Time (R/ W) (LD)

0.4

—

0.4

—

0.4

—

0.4

—

0.5

—

ns

2

Control Input Hold Time

(BWX) (NWX)

0.28

—

0.28

—

0.28

—

0.3

—

0.35

—

ns

3

Data Input Hold Time

0.28

—

0.28

—

0.28

—

0.3

—

0.35

—

ns

Notes:

1.

All Address inputs must meet the specified setup and hold times for all latching clock edges.

2.

Control signals are R/ W, LD.

3.

Control signals are BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).

4.

If C, C are tied high, K, K become the references for C, C timing parameters

5.

To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN

parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs

on the same board to be at such different voltages and temperatures.

6.

Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

7.

8.

Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands

and test setup variations.

AC Electrical Characteristics (Continued)

Parameter

Symbol

-400

-350

-333

-300

-250

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max