4M x 9 SigmaDDR-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

CQ

NC/SA

(72Mb)

SA

R/W

NC

K

NC/SA

(144Mb)

LD

SA

SA

CQ

B

NC

NC

NC

SA

NC/SA

(288Mb)

K

BW0

SA

NC

NC

DQ4

C

NC

NC

NC

SA

SA

SA

NC

NC

NC

D

NC

NC

NC

NC

NC

NC

E

NC

NC

DQ5

NC

NC

DQ3

F

NC

NC

NC

NC

NC

NC

G

NC

NC

DQ6

NC

NC

NC

H

Doff

ZQ

J

NC

NC

NC

NC

DQ2

NC

K

NC

NC

NC

NC

NC

NC

L

NC

DQ7

NC

NC

NC

DQ1

M

NC

NC

NC

NC

NC

NC

N

NC

NC

NC

SA

SA

SA

NC

NC

NC

P

NC

NC

DQ8

SA

SA

C

SA

SA

NC

NC

DQ0

R

TDO

TCK

SA

SA

SA

C

SA

SA

SA

TMS

TDI

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning

of each access.

2. BW0 controls writes to DQ0:DQ8.

3. A2, A7, and B5 are the expansion addresses.

GS8342T08/09/18/36BD-400/350/333/300/250

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02 6/2012

4/35

© 2011, GSI Technology